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TPS53632G Fiches technique(PDF) 3 Page - Texas Instruments

No de pièce TPS53632G
Description  D-CAP??Half-Bridge PWM Controller Optimized for GaN-based 48-V DC/DC Converter with I2C Interface
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TPS53632G Fiches technique(HTML) 3 Page - Texas Instruments

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background image
VFB
GFB
NC
PU3
CSP2
CSN2
CSN1
CSP1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
TPS53632G
SDA
VDD
PGOOD
NC
PWM-LO
PWM-HI
SKIP
EN
3
TPS53632G
www.ti.com
SLUSCJ3A – APRIL 2016 – REVISED JUNE 2016
Product Folder Links: TPS53632G
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
5 Pin Configuration and Functions
RSM Package
32-Pin QFN
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
COMP
26
I
Error amplifier summing node. Resistors between the VREF pin and the COMP pin (RCOMP) and
between the COMP pin and the DROOP pin (RDROOP) set the droop gain.
CSP1
17
I
Positive current sense inputs. Connect to the most positive node of current sense resistor or
inductor DCR sense network. Tie CSP2 or CSP1 (in that order) to a 3.3-V supply to disable the
phase.
CSP2
20
PU3
21
Connect to 3.3-V supply.
CSN1
18
I
Negative current sense inputs. Connect to the most negative node of current sense resistor or
inductor DCR sense network. CSN1 has a secondary OVP comparator and includes the soft-stop,
pull-down transistor.
CSN2
19
NC
22
No connect.
DROOP
25
O
Error amplifier output. A resistor pair between this pin and the VREF pin and between the COMP
pin and this pin sets the droop gain. ADROOP = 1 + RDROOP / RCOMP.
EN
8
I
Enable. 100-ns de-bounce. Regulator enters low-power mode, but retains start-up settings when
brought low.
FREQ-P
10
I
A resistor between this pin and GND sets the per-phase switching frequency. Add a resistor to
VREF to disable dynamic phase add and drop operation.
GFB
23
I
Voltage sense return. Tie to GND on PCB with a 10-Ω resistor to provide feedback when the
microprocessor is not populated.
GND
29
Analog circuit reference. Tie this pin to a quiet point on the ground plane.
IMON
13
O
Analog current monitor output. VIMON = ΣVISENSE × (1 + RIMON/ROCP).
OCP-I
12
I/O
Voltage divider to IMON. Resistor ratio sets the IMON gain (see IMON pin). A resistor between this
pin and GND (ROCP) selects 1 of 8 OCP levels (per phase, latched at start-up).
PU
9
I
Pull-up to VREF through 10-kΩ resistor.
PGOOD
3
O
Power good output. Open-drain.
PWM-HI
6
O
PWM controls for the external driver; 5-V logic level. Controller forces signal to the tri-state level
when needed.
PWM-LO
5
NC
4
No connect.
NC
30
No connect.
32


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