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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TPS544C25 Fiches technique(PDF) 7 Page - Texas Instruments |
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TPS544C25 Fiches technique(HTML) 7 Page - Texas Instruments |
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7 / 100 page  7 TPS544C25, TPS544B25 www.ti.com SLUSC81 – MAY 2015 Product Folder Links: TPS544C25 TPS544B25 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated (1) Specified by design. Not production tested. (2) The parameter covers 4.5 V to 18 V of VDD. 6.5 Electrical Characteristics TJ = –40°C to 125°C, VVIN = VVDD= 12 V, RRT = 40.2 kΩ; zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VVDD Input supply voltage range 4.5 18 V VVIN Power stage voltage range 4.5 18 IVDD Input operating current Not switching 9.5 12 mA UVLO VIN_ON Input turn on voltage Factory default setting 4.5 V Programmable range, 15 different settings 4.25 7.75 Accuracy –5% 5% VIN_OFF Input turn off voltage Factory default setting 4 V Programmable range, 15 different settings 4 7.5 Accuracy –5% 5% ERROR AMPLIFIER AND FEEDBACK VOLTAGE VFB Feedback pin voltage Default setting 940.5 950 959.5 mV Setpoint range(1) 0.5 1.5 V VFB(ACC) Feedback pin voltage accuracy VFB = 600 mV, 0°C ≤ TJ ≤ 85°C (2) –0.5% 0.5% % 0.6 V ≤ VFB ≤ 1.5 V (1) –1.0% 1.0% 0.5 V ≤ VFB < 0.6 V (1) –1.5% 1.5% AOL Open-loop gain(1) 80 dB GBWP Gain bandwidth product(1) 15 MHz IFB FB pin input bias current VFB = 0.95 V –75 75 nA ICOMP Sourcing VFB = 0 V 1 mA Sinking VFB = 1.2 V 1 VSET IVset VSET pin current 9.5 10.5 12 µA VVset Initial VOUT setting RVset = 34.8 kΩ 950 mV VVset(dis) VSET disable threshold 2.41 V OSCILLATOR FSW Adjustment range(2) 200 1000 kHz Switching frequency RRT = 40.2 kΩ 425 500 575 kHz VRMP Ramp peak-to-peak(1) VVDD/9.3 VVDD/8.5 VVDD/7.6 V VVLY Valley voltage(1) 0.75 SYNCHRONIZATION VIH(sync) High-level input voltage 2.0 V VIL(sync) Low-level input voltage 0.80 Tpw(sync) Sync input minimum pulse width 100 ns fSYNC Synchronization frequency 200 1200 kHz ΔfSYNC SYNC pin frequency range from free running frequency(1) -20% 20% RESET_B VIH(reset) High-level input voltage(1) 3.3-V and 5-V logic 2.1 V 1.8-V logic (factory default) 1.2 VIL(reset) Low-level input voltage 3.3-V and 5-V logic 0.8 1.8-V logic (factory default) 0.5 tPW(reset) Minimum RESET_B pulse width RVSET = 34.8 kΩ 200 ns Vvout_command(reset) Output voltage after reset triggered RVSET = 34.8 kΩ 950 mV |
Numéro de pièce similaire - TPS544C25 |
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Description similaire - TPS544C25 |
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