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TPS43332-Q1 Fiches technique(PDF) 6 Page - Texas Instruments |
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TPS43332-Q1 Fiches technique(HTML) 6 Page - Texas Instruments |
6 / 48 page TPS43330-Q1, TPS43332-Q1 SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014 www.ti.com 8 Specifications 8.1 Absolute Maximum Ratings (1) MIN MAX UNIT Voltage Input voltage: VIN, VBAT –0.3 60 V Ground: PGNDA–AGND, PGNDB–AGND –0.3 0.3 V Enable inputs: ENA, ENB –0.3 60 V Bootstrap inputs: CBA, CBB –0.3 68 V Bootstrap inputs: CBA–PHA, CBB–PHB –0.3 8.8 V Phase inputs: PHA, PHB –0.7 60 V Phase inputs: PHA, PHB (for 150 ns) –1 60 V Feedback inputs: FBA, FBB –0.3 13 V Voltage Error amplifier outputs: COMPA, COMPB –0.3 13 V (buck function: High-side MOSFET drivers: GA1-PHA, GB1-PHB –0.3 8.8 V BuckA and BuckB) Low-side MOSFET drivers: GA2–PGNDA, GB2–PGNDB –0.3 8.8 V Current-sense voltage: SA1, SA2, SB1, SB2 –0.3 13 V Soft start: SSA, SSB –0.3 13 V Power-good outputs: PGA, PGB –0.3 13 V Power-good delay: DLYAB –0.3 13 V Switching-frequency timing resistor: RT –0.3 13 V SYNC, EXTSUP –0.3 13 V Low-side MOSFET driver: GC1–PGNDA –0.3 8.8 V Error-amplifier output: COMPC –0.3 13 V Voltage Enable input: ENC –0.3 13 V (boost function) Current-limit sense: DS –0.3 60 V Output-voltage select: DIV –0.3 8.8 V P-channel MOSFET driver: GC2 –0.3 60 V Voltage (PMOS driver) P-channel MOSFET driver: VIN-GC2 –0.3 8.8 V Gate-driver supply, VREG –0.3 8.8 V Junction temperature, TJ –40 150 °C Operating temperature, TA –40 125 °C Storage –55 165 °C temperature, Tstg (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to AGND, unless otherwise specified. 8.2 ESD Ratings VALUE UNIT Human body model (HBM), per AEC Q100-002(1) ±2000 Electrostatic Corner pins: VBAT (1), ENC (19), SYNC (20), V(ESD) ±750 V Charged device model (CDM), per discharge VIN (38) AEC Q100-011 Other pins ±500 (1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: TPS43330-Q1 TPS43332-Q1 |
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