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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TPS4H160-Q1 Fiches technique(PDF) 9 Page - Texas Instruments |
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TPS4H160-Q1 Fiches technique(HTML) 9 Page - Texas Instruments |
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9 / 41 page  t CS(on2) t CS(off1) t CS(off2) t CS(on1) V INx I OUTx V DIAG_EN V CS V INx V OUTx t d(on) t d(off) t d(rise) t d(fall) 10% 90% 10% 90% dV/dt(on) dV/dt(off) 9 TPS4H160-Q1 www.ti.com SLVSCV8A – DECEMBER 2015 – REVISED APRIL 2016 Product Folder Links: TPS4H160-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) Value specified by design, not subject to production test 7.6 Switching Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(on) Delay time, VOUTx 10% after VINx↑ (See Figure 1.) VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, IN rising edge to 10% of VOUTx 20 50 90 µs td(off) Delay time, VOUTx 90% after VINx↓ (See Figure 1.) VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, IN falling edge to 90% of VOUTx 20 50 90 µs dV/dt(on) Turnon slew rate VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, VOUTx from 10% to 90% 0.1 0.3 0.55 V/µs dV/dt(off) Turnoff slew rate VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, VOUTx from 90% to 10% 0.1 0.3 0.55 V/µs td(match) td(rise) – td(fall) (See Figure 1.) VVS = 13.5 V, IL = 0.5A. td, rise is the IN rising edge to VOUTx = 90%. td(fall) is the IN falling edge to VOUTx = 10%. –50 50 µs CURRENT-SENSE CHARACTERISTICS (See Figure 2.) tCS(off1) CS settling time from DIAG_EN disabled(1) VVS = 13.5 V, VINx = 5 V, IOUTx = 0.5 A. current limit = 2 A. DIAG_EN falling edge to 10% of VCS. 20 µs tCS(on1) CS settling time from DIAG_EN enabled(1) VVS = 13.5 V, VINx = 5 V, IOUTx = 0.5 A. current limit is 2 A. DIAG_EN rising edge to 90% of VCS. 20 µs tCS(off2) CS settling time from IN falling edge VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A. current limit = 2 A. IN falling edge to 10% of VCS 30 100 µs tCS(on2) CS settling time from IN rising edge VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A. current limit = 2 A. IN rising edge to 90% of VCS 50 150 µs tSEx Multi-sense transition delay from channel to channel VDIAG_EN = 5 V, current sense output delay when multi- sense pins SEL and SEH transition from channel to channel 50 µs Figure 1. Output Delay Characteristics Figure 2. CS Delay Characteristics |
Numéro de pièce similaire - TPS4H160-Q1 |
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Description similaire - TPS4H160-Q1 |
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