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TPS25942LRVCT Fiches technique(PDF) 8 Page - Texas Instruments |
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TPS25942LRVCT Fiches technique(HTML) 8 Page - Texas Instruments |
8 / 54 page TPS25942A, TPS25942L, TPS25944A, TPS25944L SLVSCE9A – JUNE 2014 – REVISED MARCH 2015 www.ti.com 8.6 Timing Requirements Conditions are –40°C ≤ TJ = TA ≤ 125°C, 2.7 V ≤ V(IN) ≤ 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150 k Ω, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise noted). Refer to Figure 47 for timing diagrams. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ENABLE and UVLO INPUT EN/UVLO ↑ (100mV above V(ENR)) to V(OUT) = 100 mV, 220 µs C(dVdT) < 0.8 nF tON(dly) EN turn on delay EN/UVLO ↑ (100mV above V(ENR)) to V(OUT) = 100 mV, 100 + 150 x µs C(dVdT) ≥ 0.8 nF, see , [C(dVdT) in nF] C(dVdT) tOFF(dly) EN turn off delay EN/UVLO ↓ (100mV below V(ENF)) to FLT↓ 2 µs OVERVOLTAGE PROTECTION INPUT (OVP) tOVP(dly) OVP disable delay OVP ↑ (100mV above V(OVPR)) to FLT↓ 2 µs DIODE MODE INPUT: ACTIVE HIGH (DMODE) DMODE ↓ to (V(IN) -V(OUT)) ≤ 200 mV, with 1 A resistive DMODE turn-on delay 2 µs load at OUT tDMODE DMODE ↑ to (V(IN) -V(OUT)) > 200 mV, 1 A resistive load at DMODE turn-off delay 220 ns OUT OUTPUT RAMP CONTROL (dVdT) EN/UVLO ↑ to V(OUT) = 4.5 V, with C(dVdT) = open 0.12 tdVdT Output ramp time EN/UVLO ↑ to V(OUT) = 11 V, with C(dVdT) = open 0.25 0.37 0.5 ms EN/UVLO ↑ to V(OUT) = 11 V, with C(dVdT) = 1 nF 0.97 CURRENT LIMIT tFASTRIP(dly) Fast-Trip comparator delay I(OUT) > I(FASTRIP) 200 ns REVERSE PROTECTION COMPARATOR (V(IN) - V(OUT))↓ (1 mV overdrive below V(REVTH)) to FLT↓ 10 tREV(dly) Reverse protection comparator (V(IN) - V(OUT))↓ (10 mV overdrive below V(REVTH)) to FLT↓ 1 µs delay tFWD(dly) (V(IN) - V(OUT))↑ (10 mV overdrive above V(FWDTH)) to FLT↑ 3.1 POWER-GOOD COMPARATOR OUTPUT (PGOOD): ACTIVE HIGH TPS25942: Rising edge 0.42 0.54 0.66 tPGOODR ms PGOOD delay (de-glitch) time TPS25944: Rising edge 4 tPGOODF TPS25942 and TPS25944: Falling edge 10 µs FAULT FLAG (FLT) FLT assertion delay in Circuit TPS25944 Only; Delay from I(OUT) > I(LIM) to FLT↓ (and tCB(dly) 4 ms Breaker mode internal FET turned off) TPS25944A Only; Circuit breaker fault asserted, Delay tCB(Retrydly) Retry Delay in Circuit Breaker Mode 128 ms from to FLT ↓ to FLT↑ edge THERMAL SHUT DOWN (TSD) Retry delay in TSD TPS25942A and TPS25944A Only 128 ms 8 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: TPS25942A TPS25942L TPS25944A TPS25944L |
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