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TPS25940A Fiches technique(PDF) 3 Page - Texas Instruments |
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TPS25940A Fiches technique(HTML) 3 Page - Texas Instruments |
3 / 47 page 16 15 14 13 12 11 1 2 3 4 5 6 DEVSLP PGOOD PGTH OUT OUT OUT GND OVP EN IN IN IN Thermal Pad TPS25940A, TPS25940L www.ti.com SLVSCF3A – JUNE 2014 – REVISED MARCH 2015 6 Pin Configuration and Functions TPS25940 RVC PACKAGE (TOP VIEW) Pin Functions NAME NO. I/O DESCRIPTION DEVSLP 1 I Active High. DevSleep Mode control. A high at this pin will activate the DevSleep mode(Low Power Mode). PGOOD 2 O Active High. A high indicates PGTH has crossed the threshold value. It is an open drain output. PGTH 3 I Positive input of PGOOD comparator. OUT 4 - 8 O Power Output of the device. IN 9 - 13 I Power Input and supply voltage of the device. Input for setting programmable undervoltage lockout threshold. An undervoltage event will open internal FET and assert EN/UVLO 14 I FLT to indicate power-failure. When pulled to GND, resets the fault latch in TPS25940L. Input for setting programmable overvoltage protection threshold. An overvoltage event will open the internal FET and OVP 15 I assert FLT to indicate overvoltage. GND 16 — Ground. ILIM 17 I/O A resistor from this pin to GND sets the overload and short-circuit current limit. dVdT 18 I/O A capacitor from this pin to GND sets the ramp rate of output voltage. This pin sources a scaled down ratio of current through the internal FET. A resistor from this pin to GND converts current IMON 19 O to proportional voltage, used as analog current monitor. Fault event indicator, goes low to indicate fault condition due to Undervoltage, Overvoltage, Reverse voltage and Thermal FLT 20 O shutdown event. It is an open drain output. The GND terminal must be connected to the exposed PowerPAD. This PowerPAD must be connected to a PCB ground PowerPADTM plane using multiple vias for good thermal performance. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS25940A TPS25940L |
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