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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TPS3825-50DBVR Fiches technique(PDF) 7 Page - Texas Instruments |
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TPS3825-50DBVR Fiches technique(HTML) 7 Page - Texas Instruments |
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7 / 29 page  V IT- V DD RESET WDI t d t d t t(out) t d undefined undefined 1.1 V TPS3820, TPS3823, TPS3823A, TPS3824, TPS3825, TPS3828 www.ti.com SLVS165K – APRIL 1998 – REVISED NOVEMBER 2015 Electrical Characteristics (continued) over operating junction temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TPS382x-25 TPS382x-30 –400 Output short-circuit IOS RESET VDD = VIT, max + 0.2 V, VO = 0 V µA TPS382x-33 current(3) TPS382xA-33 TPS382x-50 –800 IDD Supply current WDI, MR, and outputs unconnected 15 25 µA Internal pullup resistor at MR 52 k Ω Ci Input capacitance at MR, WDI VI = 0 V to 5.5 V 5 pF (3) The RESET short-circuit current is the maximum pullup current when RESET is driven low by a microprocessor bidirectional reset pin. 7.6 Timing Requirements At RL = 1 MΩ, CL = 50 pF, and TJ = 25°C, unless otherwise noted. MIN TYP MAX UNIT at VDD VDD = VIT− + 0.2 V, VDD = VIT– – 0.2 V 6 μs tw Pulse width at MR VDD ≥ VIT− + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD 1 μs at WDI VDD ≥ VIT− + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD 100 ns 7.7 Switching Characteristics At RL = 1 MΩ, CL = 50 pF, and TJ = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TPS3820 112 200 300 ms VDD ≥ VIT− + 0.2 V ttout Watchdog time out See Figure 1 TPS3823/4/8, TPS3823A 0.9 1.6 2.5 s TPS3820 15 25 37 VDD ≥ VIT− + 0.2 V td Delay time ms See Figure 1 TPS3823/4/5/8, TPS3823A 120 200 300 VDD ≥ VIT− + 0.2 V, MR to RESET delay VIL = 0.3 × VDD, 0.1 (TPS3820/3/5/8, TPS3823A) Propagation (delay) time, VIH = 0.7 × VDD tPHL µs high-to-low-level output VIL = VIT– – 0.2 V, VDD to RESET delay 25 VIH = VIT– + 0.2 V VDD ≥ VIT− + 0.2 V, MR to RESET delay (TPS3824/5) VIL = 0.3 × VDD, 0.1 Propagation (delay) time, VIH = 0.7 × VDD tPLH µs low-to-high-level output VIL = VIT– – 0.2 V, VDD to RESET delay (TPS3824/5) 25 VIH = VIT– + 0.2 V Figure 1. Timing Diagram Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPS3820 TPS3823 TPS3824 TPS3825 TPS3828 |
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