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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TPS25740RGET Fiches technique(PDF) 10 Page - Texas Instruments |
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TPS25740RGET Fiches technique(HTML) 10 Page - Texas Instruments |
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10 / 64 page  10 TPS25740, TPS25740A SLVSDG8A – APRIL 2016 – REVISED MAY 2016 www.ti.com Product Folder Links: TPS25740 TPS25740A Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Electrical Characteristics (continued) Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65 V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND; VAUX, VTX, bypassed with 0.1 µF, DVDD bypassed with 0.22 µF, EN12V = GND and EN9V = GND; all other pins open (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (10) Common mode minimum aligns to VBUS UVLO. VBUS must be above its UVLO for the OCP function to be active. (11) When TJ1 trips a hard reset is transmitted and discharge is disabled, but the bleed discharge is not disabled. (12) TJ2 trips only when some external heat source drives the temperature up. When it trips the DVDD, and VAUX power outputs are turned off. OverCurrent Protection (ISNS, VBUS) VI(TRIP) Current trip shunt voltage Specified as V(ISNS)-V(VBUS). 3.5 V(10) ≤ VBUS ≤ 25 V HIPWR: 5 A not enabled 19.2 22.6 mV HIPWR = DVDD (5 A enabled) 29 34 mV OTSD TJ1 Die Temperature (Analog)(11) TJ ↑ 125 135 145 °C Hysteresis 10 TJ2 Die Temperature (Analog) (12) TJ ↑ 140 150 163 °C Hysteresis 10 7.6 Timing Requirements Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65 V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND; VAUX, VTX, bypassed with 0.1 µF, DVDD bypassed with 0.22 µF, EN12V = GND and EN9V = GND; all other pins open (unless otherwise noted) MIN NOM MAX UNIT tFOVPDG Deglitch for fast over-voltage protection 5 µs tOCP Deglitch Filter for over-current protection 15 µs Time power is applied until CC1 and CC2 pull-ups are applied. V(VPWR) > V(VPWR_TH) OR V(VDD) > V(VDD_TH) 2.5 4 ms tCC Falling/Rising voltage deglitch time for detection on CC1 and CC2 120 µs tWD Watchdog Timer, the part will automatically exit sleep mode after this time. CC pins floating 86 s Transmitter Specifications (CC1, CC2) tUI Bit unit Interval 3.05 3.3 3.70 µs Rise/fall time, tFall and tRise (refer to USB PD in Documentation Support ) External Loading per Figure 25 300 600 ns |
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