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TPS3808G18QDBVRQ1 Fiches technique(PDF) 8 Page - Texas Instruments |
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TPS3808G18QDBVRQ1 Fiches technique(HTML) 8 Page - Texas Instruments |
8 / 25 page Reset Logic Timer + − 90k V DD VDD GND 0.4 V V REF SENSE MR C T RESET R1 R 2 R 1 + R2 = 4 MW Reset Logic Timer + − 90k V DD VDD GND 0.4 V V REF SENSE MR C T RESET TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G15-Q1 TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1 SBVS085I – JANUARY 2007 – REVISED JUNE 2015 www.ti.com 8 Detailed Description 8.1 Overview The TPS3808Gxx-Q1 devices are low-current supervisory circuits used to monitor system voltages ranging from 0.4 V to 5 V. The devices assert an active low, open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin is asserted to a logic low. The RESET output remains low for the user-adjustable delay time after the SENSE voltage and MR return above their thresholds. The devices are also designed to be immune to short negative transients on the SENSE pin. The reset delay time can be configured by using the CT pin. The delay can be configured to 20 ms by leaving the CT pin floating, it can be configured to 300 ms by connecting the CT pin to VDD using a resistor, or can be configured from 1.25 ms to 10 s by connecting the CT pin to an external capacitor. 8.2 Functional Block Diagrams Figure 6. Adjustable-Voltage Version Figure 7. Fixed-Voltage Version 8 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1 TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1 |
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