Moteur de recherche de fiches techniques de composants électroniques |
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TPS3898P Fiches technique(PDF) 7 Page - Texas Instruments |
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TPS3898P Fiches technique(HTML) 7 Page - Texas Instruments |
7 / 31 page V V - IT+ hys V IT+ t pd(r) t pd(r) VCC SENSE ENABLE t d(A) V (POR) t pd(f) t d(OFF) UVLO SENSE_OUT V IT+ TPS389 www.ti.com SBVS172B – JULY 2011 – REVISED APRIL 2015 7.6 Timing Requirements MIN TYP MAX UNIT V(SENSE) rising, C(CT) = 40 µs open tpd(r) SENSE (rising) to SENSE_OUT propagation delay V(SENSE) rising, C(CT) = 190 ms 0.047 µF tpd(f) SENSE (falling) to SENSE_OUT propagation delay V(SENSE) falling 16 µs Start-up delay(1) 50 µs tw ENABLE pin minimum pulse duration 1 µs ENABLE pin glitch rejection 100 ns ENABLE to SENSE_OUT delay time (output ENABLE deasserted to td(OFF) 200 ns disabled) output deasserted ENABLE asserted to output td(P) ENABLE to SENSE_OUT delay time (P version) asserted delay 200 ns (P version) ENABLE asserted to output asserted delay 20 µs (A version), C(CT) = open td(A) ENABLE to SENSE_OUT delay time (A version) ENABLE asserted to output asserted delay 190 ms (A version), C(CT) = 0.047 µF (1) During power on, VCC must exceed 1.7 V for at least 50 µs (plus propagation delay time, tpd(r)) before output is in the correct state. Figure 1. TPS3895A and TPS3897A Timing Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPS389 |
Numéro de pièce similaire - TPS3898P |
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Description similaire - TPS3898P |
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