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TPL5010DDCT Fiches technique(PDF) 3 Page - Texas Instruments |
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TPL5010DDCT Fiches technique(HTML) 3 Page - Texas Instruments |
3 / 25 page TPL5010 VDD GND RSTn WAKE DELAY/ M_RST DONE 1 2 3 4 5 6 3 TPL5010 www.ti.com SNAS651 – JANUARY 2015 Product Folder Links: TPL5010 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated (1) G= Ground, P= Power, O= Output, I= Input. 6 Pin Configuration and Functions 6-Lead SOT23 Top View Pin Functions PIN TYPE(1) DESCRIPTION APPLICATION INFORMATION NO. NAME 1 VDD P Supply voltage 2 GND G Ground 3 DELAY/ M_RST I Time Interval set and Manual Reset Resistance between this pin and GND is used to select the time interval. The reset switch is also connected to this pin. 4 DONE I Logic Input for watchdog functionality Digital signal driven by the µC to indicate successful processing of the WAKE signal. 5 WAKE O Timer output signal generated every tIP period. Digital pulsed signal to wake up the µC at the end of the programmed time interval. 6 RSTn O Reset Output (open drain output) Digital signal to RESET the µC, pull-up resistance is required |
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Description similaire - TPL5010DDCT |
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