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TDA8024 Fiches technique(PDF) 6 Page - NXP Semiconductors |
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TDA8024 Fiches technique(HTML) 6 Page - NXP Semiconductors |
6 / 29 page 2004 July 12 6 Philips Semiconductors Product specification IC card interface TDA8024 7 PINNING Note 1. The noise margin on VCC will be higher with the 220 nF capacitor. SYMBOL PIN TYPE DESCRIPTION CLKDIV1 1 I CLK frequency selection input 1 CLKDIV2 2 I CLK frequency selection input 2 5V/3V 3 I card supply voltage selection input; VCC = 5 V (HIGH) or VCC = 3 V (LOW) PGND 4 S DC/DC converter power supply ground S2 5 I/O DC/DC converter capacitor; connected between pins S1 and S2; C = 100 nF with ESR < 100 m Ω VDDP 6 S DC/DC converter power supply voltage S1 7 I/O DC/DC converter capacitor; connected between pins S1 and S2; C = 100 nF with ESR < 100 m Ω VUP 8 I/O DC/DC converter output decoupling capacitor connection; C = 100 nF with ESR < 100 mW must be connected between VUP and PGND PRES 9 I card presence contact input (active LOW); if PRES or PRES is active, the card is considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated PRES 10 I card presence contact input (active HIGH); if PRES or PRES is active, the card is considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated I/O 11 I/O data line to/from card reader contact C7; integrated 11 k Ω pull-up resistor to VCC AUX2 12 I/O data line to/from card reader contact C8; integrated 11 k Ω pull-up resistor to VCC AUX1 13 I/O data line to/from card reader contact C4; integrated 11 k Ω pull-up resistor to VCC CGND 14 S card signal ground CLK 15 I/O card clock to/from card reader contact C3 RST 16 O card reset output from card reader contact C2 VCC 17 S card supply voltage to card reader contact C1; decoupled to CGND via 2 × 100 nF or 100 + 220 nF capacitors with ESR < 100 m Ω; note 1 PORADJ 18 I Power-on reset threshold adjustment input for changing the reset threshold with an external resistor bridge; doubles the width of the POR pulse when used; this pin is not connected for the TDA8024AT CMDVCC 19 I input from the host to start activation sequence (active LOW) RSTIN 20 I card reset input from the host VDD 21 S supply voltage GND 22 S ground OFF 23 O NMOS interrupt output to the host (active LOW); 20 k Ω integrated pull-up resistor to VDD XTAL1 24 I crystal connection or input for external clock XTAL2 25 O crystal connection (leave open-circuit if external clock source is used) I/OUC 26 I/O host data I/O line; integrated 11 k Ω pull-up resistor to VDD AUX1UC 27 I/O auxiliary data line to/from the host; integrated 11 k Ω pull-up resistor to VDD AUX2UC 28 I/O auxiliary data line to/from the host; integrated 11 k Ω pull-up resistor to VDD |
Numéro de pièce similaire - TDA8024 |
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Description similaire - TDA8024 |
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