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UC1548 Fiches technique(PDF) 3 Page - Texas Instruments

No de pièce UC1548
Description  Primary Side PWM Controller
Download  10 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

UC1548 Fiches technique(HTML) 3 Page - Texas Instruments

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UC1548
UC2548
UC3548
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Duty Cycle Clamp
Max Duty Cycle
V(DMAX) = 0.75
• VREF
73.5
76.5
79.5
%
VCC Comparator
Turn-on Threshold
13
14
V
Turn-off Threshold
910
V
Hysteresis
2.533.5
V
UV Comparator
Turn-on Threshold
4.14.354.6
V
RHYSTERESIS
Vuv = 4.2V
77
90
103
k
Reference
VREF
TA = 25
°C
4.95
5
5.05
V
0
< IO < 10mA, 12 < VCC < 20
4.93
5.07
V
Line Regulation
12V < VCC < 20V
4
15
mV
Load Regulation
0 < IO < 10mA
3
15
mV
Short Circuit Current
VREF = 0V
30
50
70
mA
Output Stage
Rise & Fall Time (Note 1)
Cl = 1nF
20
45
ns
Output Low Saturation
IO = 20mA
0.25
0.4
V
IO = 200mA
1.2
2.2
V
Output High Saturation
IO = -200mA
2.0
3.0
V
UVLO Output Low Saturation
IO = 20mA
0.8
1.2
V
ICC
ISTART
VCC = 12V
0.2
0.4
mA
ICC (pre-start)
VCC = 15V, V(UV) = 0
0.5
1
mA
ICC (run)
22
26
mA
Note 1: Guaranteed by design. Not 100% tested in production.
ELECTRICAL CHARACTERISTICS (cont.): Unless otherwise stated, all specifications are over the junction
temperature range of
−55°C to +125°C for the UC1548, −40°C to +85°C for the UC2548, and 0°C to +70°C for the UC3548. Test
conditions are: VCC = 12V, CT = 400pF, CI = 100pF, IOFF = 100
µA, CDC = 100nF, Cvs = 100pF, and Ivs = 400µA, TA = TJ.
CAO: Output of the current error amplifier. Also the
resistor load for the collector of an optocoupler.
CDC: Connect a charge balance integration capacitor
from CDC to GND to achieve an accurate duty cycle
clamp. This capacitor also sets the soft start time.
CI: Output of the inductor current waveform synthesizer.
Requires a capacitor to ground.
CT: A capacitor from CT to GND sets the oscillator
frequency.
DMAX: Programs maximum duty cycle with a resistive
divider from VREF to DMAX to GND.
GND: Signal ground.
INV: Inverting input of the current error amplifier.
IOFF: Programs the discharge slope of the capacitor on
CI to emulate the down slope of the inductor current
waveform.
ION: Input pin to inductor current waveform synthesizer.
Apply a voltage proportional to switch current to this pin.
NI: Noninverting input of the current error amplifier.
OUT: Output driver for the gate of a power FET.
PGND: Power ground pin for the output driver. This
ground circuit should be connected to GND at a single
point.
UV: Line voltage sense pin to insure the chip only
operates with sufficient line voltage. Program with a
resistive divider from the converter input voltage to UV
to GND.
VCC: Chip supply voltage. Bypass with a 1
µF ceramic
capacitor to PGND.
VREF: Precision voltage reference. Bypass with a 1
µF
ceramic capacitor to GND.
VS: Volt second clamp programming pin and feedforward
ramp waveform for the pulse width modulator. Connect a
resistor to the input line voltage and a capacitor to GND.
PIN DESCRIPTIONS
3


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