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IDT74ALVCH32373 Datasheet(Fiches technique) 1 Page - Integrated Device Technology

Numéro de pièce IDT74ALVCH32373
Description  3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD
Télécharger  7 Pages
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Fabricant  IDT [Integrated Device Technology]
Site Internet  http://www.idt.com
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IDT74ALVCH32373 Datasheet(HTML) 1 Page - Integrated Device Technology

   
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INDUSTRIALTEMPERATURERANGE
IDT74ALVCH32373
3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
1
FEBRUARY 2000
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
©2000 Integrated Device Technology, Inc.
DSC-4908/1
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
•VCC = 3.3V ± 0.3V, Normal Range
•VCC = 2.7V to 3.6V, Extended Range
•VCC = 2.5V ± 0.2V
• CMOS power levels (0.4
µµµµµ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in 96-ball LFBGA package
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for Heavy Loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
IDT74ALVCH32373
3.3V CMOS 32-BIT
TRANSPARENT D-TYPE
LATCH WITH 3-STATE
OUTPUTS AND BUS-HOLD
DESCRIPTION:
The 32-bit transparent D-type latch is built using advanced dual metal
CMOS technology. The high-speed, low-power latch is ideal for temporary
storage of data. The device can be used for implementing memory address
latches, I/O ports, and bus drivers. The Output Enable and Latch Enable
controls are organized to operate each device as four 8-bit latches, two 16-
bit latches, or one 32-bit latch. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for improved noise
margin.
The ALVCH32373 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH32373 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistor.
2
OE
D
C
2
LE
2
D1
2
Q1
H3
H4
E5
E2
4
OE
D
C
4
LE
4
D1
4
Q1
T3
T4
N5
N2
1
OE
D
C
1
LE
D1
1
Q1
TO SEVEN OTHER CHANNELS
3
OE
D
C
3
LE
3
D1
3
Q1
J3
J4
J5
J2
A3
A4
A5
A2
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS


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