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ST16C654D Fiches technique(PDF) 9 Page - Exar Corporation |
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ST16C654D Fiches technique(HTML) 9 Page - Exar Corporation |
9 / 51 page ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.0 9 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The 654 data interface supports the Intel compatible types of CPUs and it is compatible to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus transaction. Each bus cycle is asynchronous using CS# A-D, IOR# and IOW# or CS#, R/W#, A4 and A3 inputs. All four UART channels share the same data bus for host operations. A typical data bus interconnection for Intel and Motorola mode is shown in Figure 4. FIGURE 4. ST16C654/654D TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS 9&& 9&& '65$ &76$ 576$ '75$ 5;$ 7;$ 5,$ &'$ *1' $ $ $ 8$57B&6$ 8$57B&6% ,25 ,2: ' ' ' ' ' ' ' ' $ $ $ &6$ &6% ' ' ' ' ' ' ' ' ,25 ,2: 8$57 &KDQQHO $ 8$57 &KDQQHO % 8$57B,17% 8$57B,17$ ,17% ,17$ 8$57B5(6(7 5(6(7 6HULDO ,QWHUIDFH RI 56 6HULDO ,QWHUIDFH RI 56 Intel Data Bus (16 Mode) Interconnections 8$57 &KDQQHO & 8$57 &KDQQHO ' 6LPLODU WR &K $ 6LPLODU WR &K $ 6LPLODU WR &K $ 8$57B,17' 8$57B,17& ,17' ,17& 8$57B&6& 8$57B&6' &6& &6' 9&& 9&& 9&& *1' $ $ $ 8$57B&6 $ 5: ' ' ' ' ' ' ' ' $ $ $ &6$ &6% ' ' ' ' ' ' ' ' ,25 ,2: 8$57B,54 ,17% ,17$ 5(6(7 6HULDO ,QWHUIDFH RI 56 6HULDO ,QWHUIDFH RI 56 0RWRUROD 'DWD %XV 0RGH ,QWHUFRQQHFWLRQV 9&& 8$57B5(6(7 QRFRQQHFW '65$ &76$ 576$ '75$ 5;$ 7;$ 5,$ &'$ 8$57 &KDQQHO $ 8$57 &KDQQHO % 8$57 &KDQQHO & 6LPLODU WR &K $ 6LPLODU WR &K $ 6LPLODU WR &K $ ,17& QRFRQQHFW ,17' QRFRQQHFW $ &6& &6' 9&& 8$57 &KDQQHO ' |
Numéro de pièce similaire - ST16C654D |
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Description similaire - ST16C654D |
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