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ST16C654D Fiches technique(PDF) 9 Page - Exar Corporation

No de pièce ST16C654D
Description  2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
Download  51 Pages
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Fabricant  EXAR [Exar Corporation]
Site Internet  http://www.exar.com
Logo EXAR - Exar Corporation

ST16C654D Fiches technique(HTML) 9 Page - Exar Corporation

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ST16C654/654D




2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
9
2.0
FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 654 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS# A-D, IOR# and IOW# or CS#, R/W#, A4 and A3 inputs.
All four UART channels share the same data bus for host operations. A typical data bus interconnection for
Intel and Motorola mode is shown in Figure 4.
FIGURE 4. ST16C654/654D TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
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