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SN74AUP1G34DRLR Fiches technique(PDF) 10 Page - Texas Instruments |
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SN74AUP1G34DRLR Fiches technique(HTML) 10 Page - Texas Instruments |
10 / 33 page A Y SN74AUP1G34 SCES603K – AUGUST 2004 – REVISED OCTOBER 2014 www.ti.com 9 Detailed Description 9.1 Overview This single buffer gate operates from 0.8 V to 3.6 V and performs the Boolean function Y = A in positive logic. The AUP family of devices has quiescent power consumption less than 1 µA and comes in the ultra small DPW package. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back-flow through the device when it is powered. The Ioff feature also allows for live insertion. 9.2 Functional Block Diagram 9.3 Feature Description • Wide operating VCC range of 0.8 V to 3.6 V • 3.6-V I/O tolerant to support down translation • Input hysteresis allows slow input transition and better switching noise immunity at the input • Ioff feature allows voltages on the inputs and outputs when VCC is 0 V • Low noise due to slower edge rates 9.4 Device Functional Modes Table 1. Function Table INPUT OUTPUT A Y H H L L 10 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: SN74AUP1G34 |
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