5

SN74AUP1G08

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SCES502P – NOVEMBER 2003 – REVISED JUNE 2016

Product Folder Links: SN74AUP1G08

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Copyright © 2003–2016, Texas Instruments Incorporated

Pin Functions

PIN

I/O

DESCRIPTION

NAME

DRL, DCK,

DBV

DPW

DRY, DSF

YZP

YFP

A

1

2

1

A1

A1

I

Input A

B

2

1

2

B1

B1

I

Input B

DNU

–

–

–

–

B2

–

Do not use

GND

3

3

3

C1

C1

–

Ground

N.C.

–

–

5

–

–

–

No internal connection

5

5

6

A2

A2

–

Power Pin

Y

4

4

4

C2

C2

O

Output Y

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

Supply voltage

–0.5

4.6

V

–0.5

4.6

V

–0.5

4.6

V

–0.5

V

Input clamp current

–50

mA

Output clamp current

–50

mA

Continuous output current

±20

mA

±50

mA

Maximum junction temperature

150

°C

Storage temperature

–65

150

°C

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE

UNIT

Electrostatic discharge

2000

V

1000

(1)

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

Supply voltage

0.8

3.6

V

High-level input voltage

V

1.6

2