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SN74ALVCH374DWR Fiches technique(PDF) 3 Page - Texas Instruments |
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SN74ALVCH374DWR Fiches technique(HTML) 3 Page - Texas Instruments |
3 / 17 page www.ti.com RECOMMENDED OPERATING CONDITIONS (1) SN74ALVCH374 OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES118G – JULY 1997 – REVISED OCTOBER 2004 MIN MAX UNIT VCC Supply voltage 1.65 3.6 V VCC = 1.65 V to 1.95 V 0.65 × V CC VIH High-level input voltage VCC = 2.3 V to 2.7 V 1.7 V VCC = 2.7 V to 3.6 V 2 VCC = 1.65 V to 1.95 V 0.35 × V CC VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 V VCC = 2.7 V to 3.6 V 0.8 VI Input voltage 0 VCC V VO Output voltage 0 VCC V VCC = 1.65 V -4 VCC = 2.3 V -12 IOH High-level output current mA VCC = 2.7 V -12 VCC = 3 V -24 VCC = 1.65 V 4 VCC = 2.3 V 12 IOL Low-level output current mA VCC = 2.7 V 12 VCC = 3 V 24 ∆t/∆v Input transition rise or fall rate 5 ns/V TA Operating free-air temperature -40 85 °C (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 |
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