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SN74ALS533ADWRE4 Fiches technique(PDF) 1 Page - Texas Instruments

No de pièce SN74ALS533ADWRE4
Description  OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

SN74ALS533ADWRE4 Fiches technique(HTML) 1 Page - Texas Instruments

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OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
DW OR N PACKAGE
(TOP VIEW)
SN74ALS533A, SN74AS533A
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SDAS270 – DECEMBER 1994
Copyright
© 1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Eight Latches in a Single Package
3-State Bus-Driving Inverting Outputs
Full Parallel Access for Loading
Buffered Control Inputs
pnp Inputs Reduce dc Loading on
Data Lines
Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (N) 300-mil DIPs
description
These 8-bit D-type transparent latches feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads.
They
are
particularly
suitable
for
implementing
buffer
registers,
I/O
ports,
bidirectional bus drivers, and working registers.
While latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When LE is
taken low, the Q outputs are latched at the inverses of the levels set up at the D inputs. The SN74ALS533A and
SN74AS533A are functionally equivalent to the SN74ALS373A and SN74AS373, except for having inverted
outputs.
A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
The SN74ALS533A and SN74AS533A are characterized for operation from 0
°C to 70°C.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE
LE
D
Q
L
H
H
L
L
HL
H
L
LX
Q0
H
X
X
Z
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.


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