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SN74ABT3612 Fiches technique(PDF) 9 Page - Texas Instruments

No de pièce SN74ABT3612
Description  CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
Download  34 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

SN74ABT3612 Fiches technique(HTML) 9 Page - Texas Instruments

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SN74ABT3612
64
× 36 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS129G – JULY 1992 – REVISED APRIL 1998
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
empty flags (EFA, EFB)
The empty flag of a FIFO is synchronized to the port clock that reads data from its array. When the empty flag
is high, new data can be read to the FIFO output register. When the empty flag is low, the FIFO is empty and
attempted FIFO reads are ignored.
The read pointer of a FIFO is incremented each time a new word is clocked to the output register. A word written
to a FIFO can be read to the FIFO output register in a minimum of three cycles of the empty flag synchronizing
clock; therefore, an empty flag is low if a word in memory is the next data to be sent to the FIFO output register
and two cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was
written. The empty flag of the FIFO is set high by the second low-to-high transition of the synchronizing clock
and the new data word can be read to the FIFO output register in the following cycle.
A low-to-high transition on an empty flag synchronizing clock begins the first synchronization cycle of a write
if the clock transition occurs at time tsk1, or greater, after the write. Otherwise, the subsequent clock cycle can
be the first synchronization cycle (see Figures 6 and 7).
full flags (FFA, FFB)
The full flag of a FIFO is synchronized to the port clock that writes data to its array. When the full flag is high,
a memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is
low and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, the write pointer is incremented. From the time a word is read from a FIFO,
the previous memory location is ready to be written in a minimum of three cycles of the full flag synchronizing
clock; therefore, a full flag is low if less than two cycles of the full-flag synchronizing clock have elapsed since
the next memory write location has been read. The second low-to-high transition on the full-flag synchronizing
clock after the read sets the full flag high and data can be written in the following clock cycle.
A low-to-high transition on a full-flag synchronizing clock begins the first synchronization cycle of a read if the
clock transition occurs at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle can be the
first synchronization cycle (see Figures 8 and 9).
almost-empty flags (AEA, AEB)
The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The
almost-empty state is defined by the value of the almost-full and almost-empty offset register (X). This register
is loaded with one of four preset values during a device reset (see
reset). An almost-empty flag is low when the
FIFO contains X or less words in memory and is high when the FIFO contains (X + 1) or more words.
Two low-to-high transitions of the almost-empty flag synchronizing clock are required after a FIFO write for the
almost-empty flag to reflect the new level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1)
or more words remains low if two cycles of the synchronizing clock have not elapsed since the write that filled
the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of the
synchronizing clock after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of an
almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater,
after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent synchronizing clock cycle can be
the first synchronization cycle (see Figures 11 and 12).
almost-full flags (AFA, AFB)
The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The almost-full state
is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one
of four preset values during a device reset (see
reset). An almost-full flag is low when the FIFO contains (64
– X) or more words in memory and is high when the FIFO contains [64 – (X + 1)] or less words.
Two low-to-high transitions of the almost-full flag synchronizing clock are required after a FIFO read for the
almost-full flag to reflect the new level of fill; therefore, the almost-full flag of a FIFO containing [64 – (X + 1)]
or less words remains low if two cycles of the synchronizing clock have not elapsed since the read that reduced
the number of words in memory to [64 – (X + 1)]. An almost-full flag is set high by the second low-to-high


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