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SN74F138NE4 Fiches technique(PDF) 1 Page - Texas Instruments |
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SN74F138NE4 Fiches technique(HTML) 1 Page - Texas Instruments |
1 / 18 page SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051B – MARCH 1987 – REVISED JULY 1996 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems D Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception D Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description The ′F138 is designed to be used in high-performance memory-decoding or data- routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The SN54F138 is characterized for operation over the full military temperature range of – 55 °C to 125°C. The SN74F138 is characterized for operation from 0 °C to 70°C. Copyright © 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. SN54F138 ...J PACKAGE SN74F138 ...D OR N PACKAGE (TOP VIEW) SN54F138 . . . FK PACKAGE (TOP VIEW) 32 1 20 19 910 11 12 13 4 5 6 7 8 18 17 16 15 14 Y1 Y2 NC Y3 Y4 C G2A NC G2B G1 NC – No internal connection 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 A B C G2A G2B G1 Y7 GND VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. |
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