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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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SM320C26BGBM Fiches technique(PDF) 7 Page - Texas Instruments |
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SM320C26BGBM Fiches technique(HTML) 7 Page - Texas Instruments |
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7 / 42 page  SM320C26B www.ti.com SGUS069A – NOVEMBER 2012 – REVISED NOVEMBER 2012 3.3 Scaling Shifter The SM320C26B scaling shifter has a 16-bit input connected to the data bus and a 32-bit output connected to the ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed in the instruction. The LSBs of the output are filled with zeroes, and the MSBs can be either filled with zeroes or sign-extended, depending upon the status programmed into the SXM (sign-extension mode) bit of status register STO. 3.4 16 x 16-Bit Parallel Multiplier The SM320C26B has a 16 x 16-bit hardware multiplier, which is capable of computing a signed or unsigned 32-bit product in a single machine cycle. The multiplier has the following two associated registers: • A 16-bit temporary register (TR) that holds one of the operands for the multiplier, and • A 32-bit product register (PR) that holds the product. Incorporated into the SM320C26B instruction set are single-cycle multiply or accumulate instructions that allow both operands to be processed simultaneously. The data for these operations can reside anywhere in internal or external memory and can be transferred to the multiplier each cycle via the program and data buses. Four product shift modes are available at the product register (PR) output that are useful when performing multiply or accumulate operations, fractional arithmetic, or justifying fractional products. 3.5 Timer The SM320C26B provides a memory mapped 16-bit timer for control operations. The on-chip timer (TIM) register is a down counter that is continuously clocked by CLKOUT1. A timer interrupt (TINT) is generated every time the timer decrements to zero, provided the timer interrupt is enabled. The timer is reloaded with the value contained in the period (PRD) register within the next cycle after it reaches zero so that interrupts may be programmed to occur at regular intervals of PRD + 1 cycles of CLKOUT1. 3.6 Memory Control The SM320C26B provides a total of 1568 16-bit words of on-chip data RAM, divided into three separate blocks (B0, B1, and B2). Of the 1568 words, 32 words (block B2) are always data memory, and all other blocks are programmable as either data or program memory. A data memory size of 1568 words allows the SMJ320C26 to handle a data array of 1536 words, while still leaving 32 locations for intermediate storage. When using B0, B1, or B3 as program memory, instructions can be downloaded from external memory into on-chip RAM, and then executed. When using on-chip program RAM, ROM, or high-speed external program memory, the SM320C26B runs at full speed without wait states. However, the READY line can be used to interface the SM320C26B to slower, less-expensive external memory. Downloading programs from slow off-chip memory to on-chip program RAM speeds processing while cutting system costs. The SM320C26B provides three separate address spaces for program memory, data memory, and I/O. The on-chip memory is mapped into either the data memory or program memory space, depending upon the choice of memory configuration. The instruction configuration (parameter) is used as follows to configure the blocks B0, B1, and B3 as program or as data memory. Copyright © 2012, Texas Instruments Incorporated Functional Overview 7 Submit Documentation Feedback Product Folder Links: SM320C26B |
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