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LM25101A Fiches technique(PDF) 3 Page - Texas Instruments

No de pièce LM25101A
Description  Half-Bridge Gate Drivers
Download  26 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

LM25101A Fiches technique(HTML) 3 Page - Texas Instruments

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LM25101A, LM25101B, LM25101C
www.ti.com
SNVS859B – JULY 2012 – REVISED APRIL 2013
PIN DESCRIPTIONS(1)
Pin #
SO
MSOP-
Name
Description
Application Information
WSON-
WSON-
SOIC-8
Power
PowerPad
8(1)
10(1)
Pad-8
-8(1)
Positive gate
Locally decouple to VSS using low ESR/ESL
1
1
1
1
1
VDD
drive supply
capacitor located as close to the IC as possible.
Connect the positive terminal of the bootstrap
High-side gate
capacitor to HB and the negative terminal to HS. The
2
2
2
2
2
HB
driver bootstrap
bootstrap capacitor should be placed as close to the
rail
IC as possible.
High-side gate
Connect to the gate of high-side MOSFET with a
3
3
3
3
3
HO
driver output
short, low inductance path.
High-side
MOSFET
Connect to the bootstrap capacitor negative terminal
4
4
4
4
4
HS
source
and the source of the high-side MOSFET.
connection
The LM25101A/B/C inputs have TTL type thresholds.
High-side driver
5
5
5
7
5
HI
Unused inputs should be tied to ground and not left
control input
open.
The LM25101A/B/C inputs have TTL type thresholds.
Low-side driver
6
6
6
8
6
LI
Unused inputs should be tied to ground and not left
control input
open.
7
7
7
9
7
VSS
Ground return
All signals are referenced to this ground.
Low-side gate
Connect to the gate of the low-side MOSFET with a
8
8
8
10
8
LO
driver output
short, low inductance path.
EP (WSON and SO
Solder to the ground plane under the IC to aid in heat
EP
EP
EP
EP
PowerPad and MSOP-
dissipation.
PowerPad packages)
(1)
Note: For SO Power Pad - 8, WSON-8, WSON-10 and MSOP-PowerPad-8 package, it is recommended that the exposed pad on
the bottom of the package is soldered to ground plane on the PC board, and that ground plane should extend out from
beneath the IC to help dissipate heat. For WSON-10 package, pins 5 and 6 have no connection.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)
VDD to VSS
−0.3V to +18V
HB to HS
−0.3V to +18V
LI or HI Input
−0.3V to VDD +0.3V
LO Output
−0.3V to VDD +0.3V
HO Output
VHS −0.3V to VHB +0.3V
HS to VSS(2)
−5V to +100V
HB to VSS
100V
Junction Temperature
+150°C
Storage Temperature Range
−55°C to +150°C
ESD Rating, HBM(3)
2 kV
(1)
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test
conditions, see the Electrical Characteristics tables.
(2)
In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not
exceed -1V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage
transiently. If negative transients occur, the HS voltage must never be more negative than VDD-15V. For example if VDD = 10V, the
negative transients at HS must not exceed -5V.
(3)
The Human Body Model (HBM) is a 100 pF capacitor discharged through a 1.5k
Ω resistor into each pin. 2 kV for all pins except Pin 2,
Pin 3 and Pin 4 which are rated at 1000V for HBM. Machine Model (MM) rating is 100V.
Copyright © 2012–2013, Texas Instruments Incorporated
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