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AD0345BS8500RF Fiches technique(PDF) 55 Page - Texas Instruments |
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AD0345BS8500RF Fiches technique(HTML) 55 Page - Texas Instruments |
55 / 61 page 1 1 CLKOUT1 PD 2 1 CLKOUT1 TINP TOUT 2 1 1 CLKOUT1 DMAC[0:3] SMJ320C6701-SP www.ti.com SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013 DMAC, TIMER, POWER-DOWN TIMING Switching Characteristics for DMAC Outputs (see Figure 37) NO. PARAMETER MIN MAX UNIT 1 td(CKO1H–DMACV) Delay time, CLKOUT1 high to DMAC valid 2 11 ns Figure 37. DMAC Timing Timing Requirements for Timer Inputs (1) (see Figure 38) NO. MIN MAX UNIT 1 tw(TINPH) Pulse duration, TINP high 2P ns (1) P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns. Switching Characteristics for Timer Outputs (see Figure 38) NO. PARAMETER MIN MAX UNIT 2 td(CKO1H–TOUTV) Delay time, CLKOUT1 high to TOUT valid 1 10 ns Figure 38. Timer Timing Switching Characteristics for Power-Down Outputs (seeFigure 39) NO. PARAMETER MIN MAX UNIT 1 td(CKO1H–PDV) Delay time, CLKOUT1 high to PD valid 1 9 ns Figure 39. Power-Down Timing JTAG TEST-PORT TIMING Timing Requirements for JTAG Test Port (see Figure 40) Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 55 Product Folder Links: SMJ320C6701-SP |
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