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AD0345BS8500RF Fiches technique(PDF) 50 Page - Texas Instruments |
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AD0345BS8500RF Fiches technique(HTML) 50 Page - Texas Instruments |
50 / 61 page 2 1 CLKS FSR external CLKR/X (no need to resync) CLKR/X(needs resync) Bit(n-1) (n-2) (n-3) Bit 0 Bit(n-1) (n-2) (n-3) 14 13 12 11 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 CLKS CLKR FSR (int) FSR (ext) DR CLKX FSX (int) FSX (ext) FSX (XDATDLY=00b) DX 13 SMJ320C6701-SP SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013 www.ti.com Figure 31. McBSP Timing Timing Requirements for FSR When GSYNC = 1 (see Figure 32) NO. MIN MAX UNIT 1 tsu(FRH–CKSH) Setup time, FSR high before CLKS high 4(1) ns 2 th(CKSH–FRH) Hold time, FSR high after CLKS high 4(1) ns (1) This parameter is not tested. Figure 32. FSR Timing When GSYNC = 1 50 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: SMJ320C6701-SP |
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