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AD0345BS8500RF Fiches technique(PDF) 48 Page - Texas Instruments |
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AD0345BS8500RF Fiches technique(HTML) 48 Page - Texas Instruments |
48 / 61 page SMJ320C6701-SP SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013 www.ti.com MULTICHANNEL BUFFERED SERIAL PORT TIMING Timing Requirements for McBSP (1) (2) (see Figure 31) NO. MIN MAX UNIT 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P(3) ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P – 1(3) ns CLKR int 13(3) 5 tsu(FRH–CKRL) Setup time, external FSR high before CLKR low ns CLKR ext 4 CLKR int 7(3) 6 th(CKRL–FRH) Hold time, external FSR high after CLKR low ns CLKR ext 4 CLKR int 10 7 tsu(DRV–CKRL) Setup time, DR valid before CLKR low ns CLKR ext 1 CLKR int 4 8 th(CKRL–DRV) Hold time, DR valid after CLKR low ns CLKR ext 4 CLKX int 13(3) 10 tsu(FXH–CKXL) Setup time, external FSX high before CLKX low ns CLKX ext 4 CLKX int 7(3) 11 th(CKXL–FXH) Hold time, external FSX high after CLKX low ns CLKX ext 3 (1) P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns. (2) CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (3) This parameter is not tested. 48 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: SMJ320C6701-SP |
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