Moteur de recherche de fiches techniques de composants électroniques
  French  ▼

Delete All
ON OFF
ALLDATASHEET.FR

X  

Preview PDF Download HTML

AD0345BS8500RF Fiches technique(PDF) 45 Page - Texas Instruments

No de pièce AD0345BS8500RF
Description  RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Download  61 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

AD0345BS8500RF Fiches technique(HTML) 45 Page - Texas Instruments

Back Button AD0345BS8500RF Datasheet HTML 41Page - Texas Instruments AD0345BS8500RF Datasheet HTML 42Page - Texas Instruments AD0345BS8500RF Datasheet HTML 43Page - Texas Instruments AD0345BS8500RF Datasheet HTML 44Page - Texas Instruments AD0345BS8500RF Datasheet HTML 45Page - Texas Instruments AD0345BS8500RF Datasheet HTML 46Page - Texas Instruments AD0345BS8500RF Datasheet HTML 47Page - Texas Instruments AD0345BS8500RF Datasheet HTML 48Page - Texas Instruments AD0345BS8500RF Datasheet HTML 49Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 45 / 61 page
background image
SMJ320C6701-SP
www.ti.com
SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013
HOST-PORT INTERFACE TIMING
Timing Requirements for Host-Port Interface Cycles
(1) (2)
(see Figure 27, Figure 28, Figure 29, and Figure 30)
NO.
MIN
MAX
UNIT
1
tsu(SEL–HSTBL)
Setup time, select signals(3) valid before HSTROBE low
4
ns
2
th(HSTBL–SEL)
Hold time, select signals(3) valid after HSTROBE low
2
ns
3
tw(HSTBL)
Pulse duration, HSTROBE low
2P(4)
ns
4
tw(HSTBH)
Pulse duration, HSTROBE high between consecutive accesses
2P(4)
ns
10
tsu(SEL–HASL)
Setup time, select signals(3) valid before HAS low
4
ns
11
th(HASL–SEL)
Hold time, select signals(3) valid after HAS low
2
ns
12
tsu(HDV–HSTBH)
Setup time, host data valid before HSTROBE high
3
ns
13
th(HSTBH–HDV)
Hold time, host data valid after HSTROBE high
2
ns
Hold time, HSTROBE low after HRDY low. HSTROBE should
14
th(HRDYL–HSTBL)
not be inactivated until HRDY is active (low); otherwise, HPI
1(4)
ns
writes will not complete properly.
18
tsu(HASL–HSTBL)
Setup time, HAS low before HSTROBE low
2(4)
ns
19
th(HSTBL–HASL)
Hold time, HAS low after HSTROBE low
2(4)
ns
(1)
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2)
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(3)
Select signals include: HCNTRL[1:0], HR/W, and HHWIL.
(4)
This parameter is not tested.
Switching Characteristics During Host-Port Interface Cycles
(1) (2)
(see Figure 27, Figure 28, Figure 29, and Figure 30)
NO.
PARAMETER
MIN
MAX
UNIT
5
td(HCS–HRDY)
Delay time, HCS to HRDY (3)
1
12
ns
6
td(HSTBL–HRDYH)
Delay time, HSTROBE low to HRDY high(4)
1
12
ns
Output hold time, HD low impedance after HSTROBE low for an
7
toh(HSTBL–HDLZ)
4(5)
ns
HPI read
8
td(HDV–HRDYL)
Delay time, HD valid to HRDY low
P – 3(5)
P + 3(5)
ns
9
toh(HSTBH–HDV)
Output hold time, HD valid after HSTROBE high
3
12
ns
15
td(HSTBH–HDHZ)
Delay time, HSTROBE high to HD high impedance
3(5)
12(5)
ns
16
td(HSTBL–HDV)
Delay time, HSTROBE low to HD valid
3
12
ns
17
td(HSTBH–HRDYH)
Delay time, HSTROBE high to HRDY high(6)
1
12
ns
(1)
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2)
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(3)
HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI
is busy completing a previous HPID write or READ with autoincrement.
(4)
This parameter is used during an HPID read. At the beginning of the first half–word transfer on the falling edge of HSTROBE, the HPI
sends the request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into
HPID.
(5)
This parameter is not tested.
(6)
This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an
HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
Copyright © 2000–2013, Texas Instruments Incorporated
Submit Documentation Feedback
45
Product Folder Links: SMJ320C6701-SP


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61 


Fiches technique Télécharger

Go To PDF Page


Lien URL




Politique de confidentialité
ALLDATASHEET.FR
ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn