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AD0345BS8500RF Fiches technique(PDF) 42 Page - Texas Instruments |
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AD0345BS8500RF Fiches technique(HTML) 42 Page - Texas Instruments |
42 / 61 page SMJ320C6701-SP SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013 www.ti.com RESET TIMING Timing Requirements for Reset (see Figure 25) NO. MIN MAX UNIT CLKOUT Width of the RESET pulse (PLL stable)(1) 10(2) 1 1 tw(RESET) cycles Width of the RESET pulse (PLL needs to sync up)(3) 250(2) μs (1) This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable. (2) This parameter is not tested. (3) This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 μs to stabilize following device powerup or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times. Switching Characteristics During Reset (1) (see Figure 25) NO. PARAMETER MIN MAX UNIT CLKOUT1 2 tR(RESET) Response time to change of value in RESET signal 1(2) cycles 3 td(CKO1H–CKO2IV) Delay time, CLKOUT1 high to CLKOUT2 invalid –1(2) ns 4 td(CKO1H–CKO2V) Delay time, CLKOUT1 high to CLKOUT2 valid 10(2) ns 5 td(CKO1H–SDCLKIV) Delay time, CLKOUT1 high to SDCLK invalid –1(2) ns 6 td(CKO1H–SDCLKV) Delay time, CLKOUT1 high to SDCLK valid 10(2) ns 7 td(CKO1H–SSCKIV) Delay time, CLKOUT1 high to SSCLK invalid –1(2) ns 8 td(CKO1H–SSCKV) Delay time, CLKOUT1 high to SSCLK valid 10(2) ns 9 td(CKO1H–LOWIV) Delay time, CLKOUT1 high to low group invalid –1(2) ns 10 td(CKO1H–LOWV) Delay time, CLKOUT1 high to low group valid 10(2) ns 11 td(CKO1H–HIGHIV) Delay time, CLKOUT1 high to high group invalid –1(2) ns 12 td(CKO1H–HIGHV) Delay time, CLKOUT1 high to high group valid 10(2) ns 13 td(CKO1H–ZHZ) Delay time, CLKOUT1 high to Z group high impedance –1(2) ns 14 td(CKO1H–ZV) Delay time, CLKOUT1 high to Z group valid 10(2) ns (1) Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. High group consists of: HRDY and HINT. Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. (2) This parameter is not tested 42 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: SMJ320C6701-SP |
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