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AD0345BS8500RF Fiches technique(PDF) 41 Page - Texas Instruments |
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AD0345BS8500RF Fiches technique(HTML) 41 Page - Texas Instruments |
41 / 61 page DSP Owns Bus External Requester DSP Owns Bus ’C6701 Ext Req ’C6701 8 7 3 4 6 6 1 2 CLKOUT1 HOLD HOLDA EMIF Bus(1) 1 5 9 2 SMJ320C6701-SP www.ti.com SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013 HOLD/HOLDA TIMING Timing Requirements for the Hold/Hold Acknowledge Cycles (1) (see Figure 24) NO. MIN MAX UNIT 1 tsu(HOLDH–CKO1H) Setup time, HOLD high before CLKOUT1 high 5 ns 2 th(CKO1H–HOLDL) Hold time, HOLD low after CLKOUT1 high 2 ns (1) HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle. Thus, HOLD can be an asynchronous input. Switching Characteristics for the Hold/Hold Acknowledge Cycles (1) (seeFigure 24) NO. PARAMETER MIN MAX UNIT 3 tR(HOLDL–EMHZ) Response time, HOLD low to EMIF high impedance 4P (2)ns 4 tR(EMHZ–HOLDAL) Response time, EMIF high impedance to HOLDA low 2P ns 5 tR(HOLDH–HOLDAH) Response time, HOLD high to HOLDA high 4P 7P ns 6 td(CKO1H–HOLDAL) Delay time, CLKOUT1 high to HOLDA valid 1 8 ns 7 td(CKO1H–BHZ) Delay time, CLKOUT1 high to EMIF Bus high impedance(3) 1(4) 8(4) ns 8 td(CKO1H–BLZ) Delay time, CLKOUT1 high to EMIF Bus low impedance(3) 1(4) 12(4) ns 9 tR(HOLDH–BLZ) Response time, HOLD high to EMIF Bus low impedance(3) 3P 6P ns (1) P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns. (2) All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting the NOHOLD = 1. (3) EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. (4) This parameter is not tested. (1) EMIF bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. Figure 24. HOLD/HOLDA Timing Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 41 Product Folder Links: SMJ320C6701-SP |
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