Moteur de recherche de fiches techniques de composants électroniques |
|
AD0345BS8500RF Fiches technique(PDF) 37 Page - Texas Instruments |
|
AD0345BS8500RF Fiches technique(HTML) 37 Page - Texas Instruments |
37 / 61 page SMJ320C6701-SP www.ti.com SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013 SYNCHRONOUS DRAM TIMING Timing Requirements for Synchronous DRAM Cycles (see Figure 18) NO. MIN MAX UNIT 7 tsu(EDV–SDCLKH) Setup time, read EDx valid before SDCLK high 2 ns 8 th(SDCLKH–EDV) Hold time, read EDx valid after SDCLK high 3 ns Switching Characteristics for Synchronous DRAM Cycles (1) (see Figure 18 – Figure 23) NO. PARAMETER MIN MAX UNIT 1 tosu(CEV–SDCLKH) Output setup time, CEx valid before SDCLK high 1.5P – 5 ns 2 toh(SDCLKH–CEV) Output hold time, CEx valid after SDCLK high 0.5P – 1.9 ns 3 tosu(BEV–SDCLKH) Output setup time, BEx valid before SDCLK high 1.5P – 5 ns 4 toh(SDCLKH–BEIV) Output hold time, BEx invalid after SDCLK high 0.5P – 1.9 ns 5 tosu(EAV–SDCLKH) Output setup time, EAx valid before SDCLK high 1.5P – 5 ns 6 toh(SDCLKH–EAIV) Output hold time, EAx invalid after SDCLK high 0.5P – 1.9 ns 9 tosu(SDCAS–SDCLKH) Output setup time, SDCAS valid before SDCLK high 1.5P – 5 ns 10 toh(SDCLKH–SDCAS) Output hold time, SDCAS valid after SDCLK high 0.5P – 1.9 ns 11 tosu(EDV–SDCLKH) Output setup time, EDx valid before SDCLK high 1.5P – 5 ns 12 toh(SDCLKH–EDIV) Output hold time, EDx invalid after SDCLK high 0.5P – 1.9 ns 13 tosu(SDWE–SDCLKH) Output setup time, SDWE valid before SDCLK high 1.5P – 5 ns 14 toh(SDCLKH–SDWE) Output hold time, SDWE valid after SDCLK high 0.5P – 1.9 ns 15 tosu(SDA10V–SDCLKH) Output setup time, SDA10 valid before SDCLK high 1.5P – 5 ns 16 toh(SDCLKH–SDA10IV) Output hold time, SDA10 invalid after SDCLK high 0.5P – 1.9 ns 17 tosu(SDRAS–SDCLKH) Output setup time, SDRAS valid before SDCLK high 1.5P – 5 ns 18 toh(SDCLKH–SDRAS) Output hold time, SDRAS valid after SDCLK high 0.5P – 1.9 ns (1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low. Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 37 Product Folder Links: SMJ320C6701-SP |
Numéro de pièce similaire - AD0345BS8500RF |
|
Description similaire - AD0345BS8500RF |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |