Moteur de recherche de fiches techniques de composants électroniques |
|
AD0345BS8500RF Fiches technique(PDF) 35 Page - Texas Instruments |
|
AD0345BS8500RF Fiches technique(HTML) 35 Page - Texas Instruments |
35 / 61 page BE1 BE2 BE3 BE4 A1 A2 A3 A4 D1 D2 D3 D4 16 15 10 9 14 13 6 5 4 3 2 1 SSCLK CEx BE[3:0] EA[21:2] ED[31:0] SSADS SSOE SSWE SMJ320C6701-SP www.ti.com SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013 Figure 15. SBSRAM Write Timing (Full-Rate SSCLK) Timing Requirements for Synchronous-Burst SRAM Cycles (Half-Rate SSCLK) (seeFigure 16) NO. MIN MAX UNIT 7 tsu(EDV–SSCLKH) Setup time, read EDx valid before SSCLK high 3.8 ns 8 th(SSCLKH–EDV) Hold time, read EDx valid after SSCLK high 1.5 ns Switching Characteristics for Synchronous-Burst SRAM Cycles (1) (Half-Rate SSCLK) (see Figure 16 and Figure 17) NO. PARAMETER MIN MAX UNIT 1 tosu(CEV–SSCLKH) Output setup time, CEx valid before SSCLK high 1.5P – 5.5 ns 2 toh(SSCLKH–CEV) Output hold time, CEx valid after SSCLK high 0.5P – 2.3 ns 3 tosu(BEV–SSCLKH) Output setup time, BEx valid before SSCLK high 1.5P – 5.5 ns 4 toh(SSCLKH–BEIV) Output hold time, BEx invalid after SSCLK high 0.5P – 2.3 ns 5 tosu(EAV–SSCLKH) Output setup time, EAx valid before SSCLK high 1.5P – 5.5 ns 6 toh(SSCLKH–EAIV) Output hold time, EAx invalid after SSCLK high 0.5P – 2.3 ns 9 tosu(ADSV–SSCLKH) Output setup time, SSADS valid before SSCLK high 1.5P – 5.5 ns 10 toh(SSCLKH–ADSV) Output hold time, SSADS valid after SSCLK high 0.5P – 2.3 ns 11 tosu(OEV–SSCLKH) Output setup time, SSOE valid before SSCLK high 1.5P – 5.5 ns 12 toh(SSCLKH–OEV) Output hold time, SSOE valid after SSCLK high 0.5P – 2.3 ns 13 tosu(EDV–SSCLKH) Output setup time, EDx valid before SSCLK high 1.5P – 5.5 ns 14 toh(SSCLKH–EDIV) Output hold time, EDx invalid after SSCLK high 0.5P – 2.3 ns 15 tosu(WEV–SSCLKH) Output setup time, SSWE valid before SSCLK high 1.5P – 5.5 ns 16 toh(SSCLKH–WEV) Output hold time, SSWE valid after SSCLK high 0.5P – 2.3 ns (1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low. Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Links: SMJ320C6701-SP |
Numéro de pièce similaire - AD0345BS8500RF |
|
Description similaire - AD0345BS8500RF |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |