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AD0345BS8500RF Fiches technique(PDF) 31 Page - Texas Instruments |
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AD0345BS8500RF Fiches technique(HTML) 31 Page - Texas Instruments |
31 / 61 page 4 3 2 1 CLKOUT1 SSCLK SSCLK (1/2rate) CLKOUT2 SDCLK CLKOUT2 1 2 3 4 4 SMJ320C6701-SP www.ti.com SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013 Switching Characteristics for CLKOUT2 (1) (see Figure 10) NO. PARAMETER MIN MAX UNIT 1 tc(CKO2) Cycle time, CLKOUT2 2P – 0.7(2) 2P + 0.7(2) ns 2 tw(CKO2H) Pulse duration, CLKOUT2 high P – 0.7(2) P + 0.7(2) ns 3 tw(CKO2L) Pulse duration, CLKOUT2 low P – 0.7(2) P + 0.7(2) ns 4 tt(CKO2) Transition time, CLKOUT2 0.6(2) ns (1) P = 1/CPU clock frequency in ns. (2) This parameter is not tested. Figure 10. CLKOUT2 Timing SDCLK, SSCLK Timing Parameter SDCLK timing parameters are the same as CLKOUT2 parameters. SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK configuration. Switching Characteristics for the Relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1 (see Figure 11) NO. PARAMETER MIN MAX UNIT 1 td(CKO1–SSCLK) Delay time, CLKOUT1 edge to SSCLK edge –0.8 3.4 ns 2 td(CKO1–SSCLK1/2) Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate) –1 3 ns 3 td(CKO1–CKO2) Delay time, CLKOUT1 edge to CLKOUT2 edge –1.5 2.5 ns 4 td(CKO1–SDCLK) Delay time, CLKOUT1 edge to SDCLK edge –1.5 1.9 ns Figure 11. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1 Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Links: SMJ320C6701-SP |
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