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AD0345BS8500RF Fiches technique(PDF) 25 Page - Texas Instruments |
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AD0345BS8500RF Fiches technique(HTML) 25 Page - Texas Instruments |
25 / 61 page CLKMODE0 CLKMODE1 PLL PLLV CLKIN LOOP FILTER PLLCLK PLLMULT CLKIN Internal to ’C6701 CPU CLOCK 1 0 3.3V See Table 3 PLLFREQ1 PLLFREQ2 PLLFREQ3 CLKMODE0 CLKMODE1 PLL PLLV CLKIN LOOP FILTER PLLCLK PLLMULT CLKIN C2 Internal to ’C6701 CPU CLOCK C1 R1 3.3V 10 mF 0.1 mF C3 C4 1 0 See Table 3 PLLFREQ1 PLLFREQ2 PLLFREQ3 SMJ320C6701-SP www.ti.com SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013 AVAILABLE MULTIPLY FACTORS CPU CLOCK FREQUENCY CLKMODE1 CLKMODE0 PLL MULTIPLY FACTORS F(CPUCLOCK) 0 1 Reserved Reserved 1 0 Reserved Reserved 1 1 x4 4 x f(CLKIN) (1) Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition, place all PLL external components (R1, C1, C2, C3, C4, and the EMI filter) as close to the ’C6000 device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. (2) For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4, and the EMI filter). (3) The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. Figure 5. External PLL Circuitry for Either PLL ×4 Mode or ×1 (Bypass) Mode (1) For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal. (2) The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. Figure 6. External PLL Circuitry for ×1 (Bypass) Mode Only Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Links: SMJ320C6701-SP |
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