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AD0345BS8500RF Fiches technique(PDF) 24 Page - Texas Instruments

No de pièce AD0345BS8500RF
Description  RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR
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SMJ320C6701-SP
SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013
www.ti.com
The TMS320C6x Evaluation Module Reference Guide (literature number SPRU269) provides instructions for
installing and operating the ’C6x evaluation module. It also includes support software documentation, application
programming interfaces, and technical reference material.
TMS320C6000 DSP/BIOS User’s Guide (literature number SPRU303) describes how to use DSP/BIOS tools and
APIs to analyze embedded real-time DSP applications.
Code Composer User’s Guide (literature number SPRU296) explains how to use the Code Composer
development environment to build and debug embedded real-time DSP applications.
Code Composer Studio Tutorial (literature number SPRU301) introduces the Code Composer Studio integrated
development environment and software tools.
The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the ’C62x/C67x
devices, associated development tools, and third-party support.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and
education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to update
SMJ320 customers on product information. The TMS320 DSP bulletin board service (BBS) provides access to
information pertaining to the SMJ320 family, including documentation, source code, and object code for many
DSP algorithms and utilities. The BBS can be reached at 281/274-2323.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
Clock PLL
All of the internal ’C67x clocks are generated from a single source through the CLKIN pin. This source clock
either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Table 3,
Table 4, and Figure 5 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes.
Table 3 and Figure 6 show the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
To minimize the clock jitter, a single clean power supply should power both the ’C67x device and the external
clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum CLKIN rise and
fall times should also be observed. For the input clock timing requirements, see the input and output clocks
electricals section. Guidelines for EMI filter selection are as follows: maximum attenuation frequency = 20–30
MHz, maximum dB attenuation = 45–50 dB, and minimum dB attenuation above 30 MHz = 20 dB.
Table 3. CLKOUT1 Frequency Ranges(1)
PLLFREQ3
PLLFREQ2
PLLFREQ1
CLKOUT1 FREQUENCY RANGE
(C13)
(G11)
(F11)
(MHz)
0
0
0
50-140
(1)
Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1
frequency. Choose the lowest frequency range that includes the desired frequency. For example, for CLKOUT1 = 133 MHz, choose
PLLFREQ value of 000b. PLLFREQ values other than 000b, 001b, and 010b are reserved.
Table 4. 'C6701 PLL Component Selection Table
CPU CLOCK
CLKIN
TYPICAL
FREQUENCY
CLKOUT2 RANGE
R1
C1
C2
CLKMODE
RANGE
LOCK TIME
(CLKOUT1)
(MHz)
(W)
(nF)
(pF)
(MHz)
(
μs)(1)
RANGE (MHz)
x4
12.5 – 41.7
50-140
25 – 83.5
60.4
27
560
75
(1)
Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For
example, if the typical lock time is specified as 100
μs, the maximum value may be as long as 250 μs.
AVAILABLE MULTIPLY FACTORS
CPU CLOCK FREQUENCY
CLKMODE1
CLKMODE0
PLL MULTIPLY FACTORS
F(CPUCLOCK)
0
0
x1(BYPASS)
1 x f(CLKIN)
24
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Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: SMJ320C6701-SP


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