Moteur de recherche de fiches techniques de composants électroniques
  French  ▼

Delete All
ON OFF
ALLDATASHEET.FR

X  

Preview PDF Download HTML

AD0345AS8500RF Fiches technique(PDF) 55 Page - Texas Instruments

No de pièce AD0345AS8500RF
Description  RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Download  61 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

AD0345AS8500RF Fiches technique(HTML) 55 Page - Texas Instruments

Back Button AD0345AS8500RF Datasheet HTML 51Page - Texas Instruments AD0345AS8500RF Datasheet HTML 52Page - Texas Instruments AD0345AS8500RF Datasheet HTML 53Page - Texas Instruments AD0345AS8500RF Datasheet HTML 54Page - Texas Instruments AD0345AS8500RF Datasheet HTML 55Page - Texas Instruments AD0345AS8500RF Datasheet HTML 56Page - Texas Instruments AD0345AS8500RF Datasheet HTML 57Page - Texas Instruments AD0345AS8500RF Datasheet HTML 58Page - Texas Instruments AD0345AS8500RF Datasheet HTML 59Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 55 / 61 page
background image
1
1
CLKOUT1
PD
2
1
CLKOUT1
TINP
TOUT
2
1
1
CLKOUT1
DMAC[0:3]
SMJ320C6701-SP
www.ti.com
SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013
DMAC, TIMER, POWER-DOWN TIMING
Switching Characteristics for DMAC Outputs
(see Figure 37)
NO.
PARAMETER
MIN
MAX
UNIT
1
td(CKO1H–DMACV)
Delay time, CLKOUT1 high to DMAC valid
2
11
ns
Figure 37. DMAC Timing
Timing Requirements for Timer Inputs
(1)
(see Figure 38)
NO.
MIN
MAX
UNIT
1
tw(TINPH)
Pulse duration, TINP high
2P
ns
(1)
P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
Switching Characteristics for Timer Outputs
(see Figure 38)
NO.
PARAMETER
MIN
MAX
UNIT
2
td(CKO1H–TOUTV)
Delay time, CLKOUT1 high to TOUT valid
1
10
ns
Figure 38. Timer Timing
Switching Characteristics for Power-Down Outputs
(seeFigure 39)
NO.
PARAMETER
MIN
MAX
UNIT
1
td(CKO1H–PDV)
Delay time, CLKOUT1 high to PD valid
1
9
ns
Figure 39. Power-Down Timing
JTAG TEST-PORT TIMING
Timing Requirements for JTAG Test Port
(see Figure 40)
Copyright © 2000–2013, Texas Instruments Incorporated
Submit Documentation Feedback
55
Product Folder Links: SMJ320C6701-SP


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61 


Fiches technique Télécharger

Go To PDF Page


Lien URL




Politique de confidentialité
ALLDATASHEET.FR
ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn