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AD0345AS8500RF Fiches technique(PDF) 44 Page - Texas Instruments

No de pièce AD0345AS8500RF
Description  RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
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AD0345AS8500RF Fiches technique(HTML) 44 Page - Texas Instruments

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Interrupt Number
6
5
4
4
3
2
CLKOUT2
EXT_INTx, NMI
1
Intr Flag
IACK
INUMx
SMJ320C6701-SP
SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013
www.ti.com
EXTERNAL INTERRUPT/RESET TIMING
Timing Requirements for Interrupt Response Cycles
(1) (2)
(see Figure 26)
NO.
MIN
MAX
UNIT
2
tw(ILOW)
Width of the interrupt pulse low
2P(3)
ns
3
tw(IHIGH)
Width of the interrupt pulse high
2P(3)
ns
(1)
Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus,
they can be connected to asynchronous inputs.
(2)
P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(3)
This parameter is not tested.
Switching Characteristics During Interrupt Response Cycles
(1)
(see Figure 26)
NO.
PARAMETER
MIN
MAX
UNIT
1
tR(EINTH–IACKH)
Response time, EXT_INTx high to IACK high
9P
ns
4
td(CKO2L–IACKV)
Delay time, CLKOUT2 low to IACK valid
–0.5P
13 – 0.5P
ns
5
td(CKO2L–INUMV)
Delay time, CLKOUT2 low to INUMx valid
10 – 0.5P
ns
6
td(CKO2L–INUMIV)
Delay time, CLKOUT2 low to INUMx invalid
–0.5P
ns
(1)
P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
When the PLL is used (CLKMODE x4), 0.5P = 1/(2 x CPU clock frequency).
For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN.
Figure 26. Interrupt Timing
44
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Product Folder Links: SMJ320C6701-SP


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