Moteur de recherche de fiches techniques de composants électroniques
  French  ▼

Delete All
ON OFF
ALLDATASHEET.FR

X  

Preview PDF Download HTML

AD0345AS8500RF Fiches technique(PDF) 31 Page - Texas Instruments

No de pièce AD0345AS8500RF
Description  RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Download  61 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

AD0345AS8500RF Fiches technique(HTML) 31 Page - Texas Instruments

Back Button AD0345AS8500RF Datasheet HTML 27Page - Texas Instruments AD0345AS8500RF Datasheet HTML 28Page - Texas Instruments AD0345AS8500RF Datasheet HTML 29Page - Texas Instruments AD0345AS8500RF Datasheet HTML 30Page - Texas Instruments AD0345AS8500RF Datasheet HTML 31Page - Texas Instruments AD0345AS8500RF Datasheet HTML 32Page - Texas Instruments AD0345AS8500RF Datasheet HTML 33Page - Texas Instruments AD0345AS8500RF Datasheet HTML 34Page - Texas Instruments AD0345AS8500RF Datasheet HTML 35Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 31 / 61 page
background image
4
3
2
1
CLKOUT1
SSCLK
SSCLK (1/2rate)
CLKOUT2
SDCLK
CLKOUT2
1
2
3
4
4
SMJ320C6701-SP
www.ti.com
SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013
Switching Characteristics for CLKOUT2
(1)
(see Figure 10)
NO.
PARAMETER
MIN
MAX
UNIT
1
tc(CKO2)
Cycle time, CLKOUT2
2P – 0.7(2) 2P + 0.7(2)
ns
2
tw(CKO2H)
Pulse duration, CLKOUT2 high
P – 0.7(2)
P + 0.7(2)
ns
3
tw(CKO2L)
Pulse duration, CLKOUT2 low
P – 0.7(2)
P + 0.7(2)
ns
4
tt(CKO2)
Transition time, CLKOUT2
0.6(2)
ns
(1)
P = 1/CPU clock frequency in ns.
(2)
This parameter is not tested.
Figure 10. CLKOUT2 Timing
SDCLK, SSCLK Timing Parameter
SDCLK timing parameters are the same as CLKOUT2 parameters.
SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK
configuration.
Switching Characteristics for the Relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1
(see Figure 11)
NO.
PARAMETER
MIN
MAX
UNIT
1
td(CKO1–SSCLK)
Delay time, CLKOUT1 edge to SSCLK edge
–0.8
3.4
ns
2
td(CKO1–SSCLK1/2)
Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate)
–1
3
ns
3
td(CKO1–CKO2)
Delay time, CLKOUT1 edge to CLKOUT2 edge
–1.5
2.5
ns
4
td(CKO1–SDCLK)
Delay time, CLKOUT1 edge to SDCLK edge
–1.5
1.9
ns
Figure 11. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1
Copyright © 2000–2013, Texas Instruments Incorporated
Submit Documentation Feedback
31
Product Folder Links: SMJ320C6701-SP


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61 


Fiches technique Télécharger

Go To PDF Page


Lien URL




Politique de confidentialité
ALLDATASHEET.FR
ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn