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AD0345AS8500RF Fiches technique(PDF) 26 Page - Texas Instruments
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AD0345AS8500RF Fiches technique(HTML) 26 Page - Texas Instruments
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SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time if the other
supply is below the proper operating voltage.
System-Level Design Considerations
System-level design considerations, such as bus contention, may require supply sequencing to be implemented.
In this case, the core supply should be powered up at the same time as, or prior to (and powered down after),
the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers
are powered up, thus, preventing bus contention with other chips on the board.
Power-Supply Design Considerations
For systems using the C6000™ DSP platform of devices, the core supply may be required to provide in excess
of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic
within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the I/O
supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the PLL
disabled, an external clock pulse may be required to stop this extra current draw. A normal current state returns
once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing the amount of time between
the core supply power up and the I/O supply power up can minimize the effects of this current draw.
A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx plug-
in power modules, can be used to eliminate the delay between core and I/O power up [see the Using the
TPS56300 to Power DSPs application report (literature number SLVA088)]. A Schottky diode can also be used to
tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the logic
within the DSP.
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000™ platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
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