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ADCS7476AIMF Fiches technique(PDF) 9 Page - National Semiconductor (TI) |
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ADCS7476AIMF Fiches technique(HTML) 9 Page - National Semiconductor (TI) |
9 / 22 page Timing Test Circuit 20057708 ADCS7476/ADCS7477/ADCS7478 Timing Specifications The following specifications apply for V DD = +2.7V to 5.25V, fSCLK = 20 MHz, Boldface limits apply for TA = −40˚C to +85˚C: all other limits T A = 25˚C, unless otherwise noted. (Note 9) Symbol Parameter Conditions Typical Limits Units t CONVERT 16xt SCLK t QUIET (Note 5) 50 ns (min) t 1 Minimum CS Pulse Width 10 ns (min) t 2 CS to SCLK Setup Time 10 ns (min) t 3 Delay from CS Until SDATA TRI-STATE® Disabled (Note 6) 20 ns (max) t 4 Data Access Time after SCLK Falling Edge(Note 7) V DD = +2.7 to +3.6 40 ns (max) V DD = +4.75 to +5.25 20 ns (max) t 5 SCLK Low Pulse Width 0.4 x t SCLK ns (min) t 6 SCLK High Pulse Width 0.4 x t SCLK ns (min) t 7 SCLK to Data Valid Hold Time V DD = +2.7 to +3.6 7 ns (min) V DD = +4.75 to +5.25 5 ns (min) t 8 SCLK Falling Edge to SDATA High Impedance (Note 8) V DD = +2.7 to +3.6 25 ns (max) 6 ns (min) V DD = +4.75 to +5.25 25 ns (max) 5 ns (min) t POWER-UP Power-Up Time from Full Power-Down 1µs Note 5: Minimum Quiet Time Required Between Bus Relinquish and Start of Next Conversion Note 6: Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V. Note 7: Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V or 2.0V. Note 8: t8 is derived from the time taken by the outputs to change by 0.5V with the loading circuit shown above. The measured number is then adjusted to remove the effects of charging or discharging the 25pF capacitor. This means t8 is the true bus relinquish time, independent of the bus loading. Note 9: All input signals are specified as tr =tf = 5 ns (10% to 90% VDD) and timed from 1.6V. www.national.com 9 |
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