Moteur de recherche de fiches techniques de composants électroniques |
|
CDCVF2510A Fiches technique(PDF) 6 Page - Texas Instruments |
|
|
CDCVF2510A Fiches technique(HTML) 6 Page - Texas Instruments |
6 / 18 page SWITCHING CHARACTERISTICS From Output Under Test LOAD CIRCUIT FOR OUTPUTS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tpd 50% VCC 3 V 0 V VOH VOL Input 0.4 V 2 V tr tf 0.4 V 2 V Output 500 W 50% VCC 25 pF NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 133 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns. C. The outputs are measured one at a time with one transition per measurement. CDCVF2510A SCAS764C – MARCH 2004 – REVISED FEBRUARY 2009 ............................................................................................................................................... www.ti.com over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF (see Note (1) and Figure 1 and Figure 2) (2) VCC, AVCC = 3.3 V FROM TO ± 0.3 V PARAMETER UNIT (INPUT) (OUTPUT) MIN TYP MAX CLK ↑ = 25 MHz to 65 MHz –150 150 Phase error time-static (normalized) t(φ) FBIN ↑ ps (see Figure 4 through Figure 7) CLK ↑ = 66 MHz to 175 MHz –125 125 tsk(o) Output skew time(3) Any Y Any Y 100 ps Phase error time-jitter (4) CLK = 66 MHz to 175 MHz Any Y or FBOUT –50 50 ps CLK = 25 MHz to 40 MHz 500 Jitter(cycle-cycle)(see Figure 8) CLK = 41 MHz to 59 MHz Any Y or FBOUT 200 ps CLK = 60 MHz to 175 MHz 65 125 CLK ↑ = 25 MHz to 65 MHz 1.5 td(φ) Dynamic phase offset(5) FBIN ↑ ns CLK ↑ = 66 MHz to 175 MHz 0.4 Duty cycle f(CLK) > 60 MHz Any Y or FBOUT 45% 55% tr Rise time VO = 0.4 V to 2 V Any Y or FBOUT 0.3 1.1 ns/V tf Fall time VO = 2 V to 0.4 V Any Y or FBOUT 0.3 1.1 ns/V Low-to-high propagation delay time, bypass tPLH CLK Any Y or FBOUT 1.8 3.9 ns mode High-to-low propagation delay time, bypass tPHL CLK Any Y or FBOUT 1.8 3.9 ns mode (1) The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. (2) These parameters are not production tested. (3) The tsk(o) specification is only valid for equal loading of all outputs. (4) Calculated per PC DRAM SPEC (tphase error, static - jitter(cycle-to-cycle)). (5) The parameter is assured by design but cannot be 100% production tested. PARAMETER MEASUREMENT INFORMATION Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): CDCVF2510A |
Numéro de pièce similaire - CDCVF2510A |
|
Description similaire - CDCVF2510A |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |