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CDCV855IPWRG4 Fiches technique(PDF) 5 Page - Texas Instruments |
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CDCV855IPWRG4 Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 15 page CDCV855, CDCV855I 2.5-V PHASE-LOCK LOOP CLOCK DRIVER SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT tPLH} Low-to-high level propagation delay time Test mode/CLK to any output 4.5 ns tPHL} High-to-low level propagation delay time Test mode/CLK to any output 4.5 ns t ()§ Jitter (period) See Figure 5 66 MHz –55 55 ps tjit(per)§ Jitter (period), See Figure 5 100/133/167/180 MHz –35 35 ps t ()§ Jitter (cycle to cycle) See Figure 2 66 MHz –60 60 ps tjit(cc)§ Jitter (cycle-to-cycle), See Figure 2 100/133/167/180 MHz –50 50 ps 66 MHz –130 130 tjit(hper)§ Half-period jitter, See Figure 6 100 MHz –90 90 ps tjit(h er) Half eriod jitter, See Figure 6 133/167/180 MHz –75 75 s t Output clock slew rate See Figure 7 Load = 120 Ω / 14 pF 1 2 V/ns tslr(o) Output clock slew rate, See Figure 7 Load = 120 Ω / 4 pF 1 3 V/ns 66 MHz –180 180 SSC off 100/133 MHz –130 130 t w Dynamic phase offset (this includes jitter), SSC off 167/180 MHz –90 90 ps td(Ø)w Dynamic hase offset (this includes jitter), See Figure 3(b) 66 MHz –230 230 ps SSC on 100/133 MHz –170 170 SSC on 167/180 MHz –100 100 t Static phase offset See Figure 3(a) 66 MHz –150 150 ps t(Ø) Static phase offset, See Figure 3(a) 100/133/167/180 MHz –100 100 ps tsk(o)¶ Output skew, See Figure 4 50 ps tr, tf Output rise and fall times (20% – 80%) Load: 120 Ω/14 pF 650 900 ps † All typical values are at a respective nominal VDDQ. ‡ Refers to transition of noninverting output § This parameter is assured by design but can not be 100% production tested. ¶ All differential output pins are terminated with 120 Ω/14 pF. |
Numéro de pièce similaire - CDCV855IPWRG4 |
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Description similaire - CDCV855IPWRG4 |
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