CDCM7005-SP_16 datasheet(6/49 Pages) TI1

No de pièce	CDCM7005-SP

Description	CDCM7005-SP 3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and Jitter Cleaner

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Fabricant	TI1 [Texas Instruments]

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6

CDCM7005-SP

SGLS390G – JULY 2009 – REVISED NOVEMBER 2015

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Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

CTRL_LE

5

I

LVCMOS input, control latch enable for serial programmable Interface (SPI), with

hysteresis. Unused or floating inputs must be tied to proper logic level. It is

recommended to use a 20-k

Ω or larger pullup resistor to VCC.

CTRL_CLK

4

I

LVCMOS input, serial control clock input for SPI, with hysteresis. Unused or floating

inputs must be tied to proper logic level. It is recommended to use a 20-k

Ω or larger

pullup resistor to VCC.

CTRL_DATA

2

I

LVCMOS input, serial control data input for SPI, with hysteresis. Unused or floating

inputs must be tied to proper logic level. It is recommended to use a 20-k

Ω or larger

pullup resistor to VCC.

PD

27

I

LVCMOS input, asynchronous power down (PD) signal. This pin is low active and can

be activated external or by the corresponding bit in the SPI register (in case of logic

high, the SPI setting is valid). Switches the device into power-down mode. Resets M-

and N-Divider, 3-states charge pump, STATUS_REF, or PRI_SEC_CLK pin,

STATUS_VCXO or I_REF_CP pin, PLL_LOCK pin, VBB pin and all Yx outputs. Sets the

SPI register to default value; has internal 150-k

Ω pullup resistor.

It is recommended to ramp up the PD with the same time as VCC and AVCC or later. The

ramp up rate of the PD should not be faster than the ramp up rate of VCC and AVCC.

RESET or

HOLD

40

I

This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET is the

default function. This pin is low active and can be activated external or via the

corresponding bit in the SPI register. In case of RESET, the charge pump (CP) is

switched to 3-state and all counters (N, M, P) are reset to zero (the initial divider settings

are maintained in SPI registers). The LVPECL outputs are static low and high

respectively and the LVCMOS outputs are all low or high if inverted. RESET is not edge

triggered and should have a pulse duration of at least 5 ns.

In case of HOLD, the CP is switched in to 3-state mode only. After HOLD is released

and with the next valid reference clock cycle the charge pump is switched back in to

normal operation (CP stays in 3-state as long as no reference clock is valid). During

HOLD, the P divider and all outputs Yx are at normal operation. This mode allows an

external control of the frequency hold-over mode.

The input has an internal 150-k

Ω pullup resistor.

VCXO_IN

21

I

VCXO LVPECL input

VCXO_IN

20

I

Complementary VCXO LVPECL input

PRI_REF

14

I

LVCMOS input for the primary reference clock, with an internal 150-k

Ω pullup resistor

and input hysteresis.

SEC_REF

15

I

LVCMOS input for the secondary reference clock, with an internal 150-k

Ω pullup resistor

and input hysteresis.

REF_SEL

12

I

LVCMOS reference clock selection input. In the manual mode the REF_SEL signal

selects one of the two input clocks:

REF_SEL [1]: PRI_REF is selected;

REF_SEL [0]: SEC_REF is selected;

The input has an internal 150-k

Ω pullup resistor.

CP_OUT

8

O

Charge pump output

VBB

18

O

Bias voltage output to be used to bias unused complementary input VCXO_IN for single

ended signals. The output of VBB is VCC – 1.3 V. The output current is limited to about

1.5 mA.

STATUS_REF or

PRI_SEC_CLK

50

O

This output can be programmed (SPI) to provide either the STATUS_REF or

PRI_SEC_CLK information. This pin is set high if one of the STATUS conditions is valid.

STATUS_REF is the default setting.

In case of STATUS_REF, the LVCMOS output provides the Status of the Reference

Clock. If a reference clock with a frequency above 2 MHz is provided to PRI_REF or

SEC_REF STATUS_REF will be set high.

In case of PRI_SEC_CLK, the LVCMOS output indicates whether the primary clock

[high] or the secondary clock [low] is selected.

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