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AD1980JST Datasheet(Fiches technique) 4 Page - Analog Devices

Numéro de pièce AD1980JST
Description  AC ’97 SoundMAX Codec
Télécharger  32 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD1980JST Datasheet(HTML) 4 Page - Analog Devices

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REV. 0
–4–
AD1980
Parameter
PR[K:I]
1
PR[6:0]
1
DVDD Typ
AVDD Typ
Unit
POWER-DOWN STATES
2
Fully Active
000
000 0000
53
70
mA
ADC
000
000 0001
44
66
mA
FRONT DAC
000
000 0010
46
61
mA
SURROUND DAC
010
000 0000
46
61
mA
CENTER/LFE DAC
101
000 0000
46
61
mA
ADC + ALL DACs
111
000 0011
12
33
mA
Mixer
000
000 0100
52
44
mA
ADC + Mixer
000
000 0101
45
39
mA
ALL DACs + Mixer
111
000 0110
31
14
mA
ADC + ALL DACs + Mixer
111
000 0111
12
8
mA
Standby
111
011 1111
0
0
mA
Headphone Standby
000
100 0000
52
65
mA
NOTES
1PR bits are controlled in Reg. 2Ah and 26h
2Values presented with V
REFOUT loaded.
Specifications subject to change without notice.
Parameter
Symbol
Min
Typ
Max
Unit
RESET Active Low Pulsewidth
tRST_LOW
1.0
µs
RESET Inactive to BIT_CLK Startup Delay
tRST2CLK
162.8
400,000
ns
SYNC Active High Pulsewidth
tSYNC_HIGH
1.3
µs
SYNC Low Pulsewidth
tSYNC_LOW
19.5
µs
SYNC Inactive to BIT_CLK Startup Delay
tSYNC2CLK
162.8
ns
BIT_CLK Frequency
12.288
MHz
BIT_CLK Frequency Accuracy
1.0
ppm
BIT_CLK Period
tCLK_PERIOD
81.4
ns
BIT_CLK Output Jitter
1, 2
750
ps
BIT_CLK High Pulsewidth
tCLK_HIGH
40
41.7
ns
BIT_CLK Low Pulsewidth
tCLK_LOW
39.7
41.4
ns
SYNC Frequency
48.0
kHz
SYNC Period
tSYNC_PERIOD
20.8
µs
Setup to Falling Edge of BIT_CLK
tSETUP
4ns
Hold from Falling Edge of BIT_CLK
tHOLD
3ns
BIT_CLK Rise Time
tRISECLK
24
6
ns
BIT_CLK Fall Time
tFALLCLK
24
6
ns
SYNC Rise Time
tRISESYNC
24
6
ns
SYNC Fall Time
tFALLSYNC
24
6
ns
SDATA_IN Rise Time
tRISEDIN
24
6
ns
SDATA_IN Fall Time
tFALLDIN
24
6
ns
SDATA_OUT Rise Time
tRISEDOUT
24
6
ns
SDATA_OUT Fall Time
tFALLDOUT
24
6
ns
End of Slot 2 to BIT_CLK, SDATA_IN Low
tS2_PDOWN
0
1.0
µs
Setup to RESET Inactive (SYNC, SDATA_OUT)
tSETUP2RST
15
ns
Rising Edge of RESET to Hi-Z Delay
tOFF
25
ns
Propagation Delay
15
ns
RESET Rise Time
50
ns
Output Valid Delay from BIT_CLK Rising
15
ns
NOTES
1Guaranteed but not tested.
2Output jitter directly dependent on crystal input jitter.
Specifications subject to change without notice.
TIMING PARAMETERS (Guaranteed over Operating Temperature Range)
Parameter
Min
Typ
Max
Unit
CLOCK SPECIFICATIONS
*
Input Clock Frequency (XTAL Mode or Clock Oscillator)
24.576
MHz
Input Clock Frequency (Reference Clock Mode)
14.31818
MHz
Input Clock Frequency (USB Clock Mode)
48.000
MHz
Recommended Clock Duty Cycle
40
50
60
%
*Guaranteed but not tested.
Specifications subject to change without notice.


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