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CDCLVD110VF Fiches technique(PDF) 4 Page - Texas Instruments |
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CDCLVD110VF Fiches technique(HTML) 4 Page - Texas Instruments |
4 / 13 page www.ti.com JITTER CHARACTERISTICS LVDS — SWITCHING CHARACTERISTICS CONTROL REGISTER CHARACTERISTICS CDCLVD110 SCAS684C – SEPTEMBER 2002 – REVISED JANUARY 2008 ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RECEIVER VIDH Input threshold high 100 mV VIDL Input threshold low –100 mV |VID| Input differential voltage 200 mV IIH VI = VDD Input current, CLK0/CLK0, CLK1/CLK1 –5 5 µA IIL VI = 0 V CI Input capacitance VI = VDD or GND 3 pF SUPPLY CURRENT Full loaded All outputs enabled and loaded, RL = 100 Ω, f = 0 Hz 130 IDD Supply current No load Outputs enabled, no output load, f = 0 Hz 35 mA IDDZ 3-State All outputs 3-state by control logic, f = 0 Hz 35 characterized with CDCLVD110 performance EVM, VDD = 3.3 V, OUTPUTS NOT UNDER TEST are terminated to 50Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 12 kHz to 5 MHz, fout = 30.72 MHz 650 Additive phase jitter from input to tjitterLVDS fs rms LVDS output Q3 and Q3 12 kHz to 20 MHz, fout = 125 MHz 299 over recommended operating free-air temperature range, VDD = 2.5 V ±5% FROM TO PARAMETER MIN TYP MAX UNIT (INPUT) (OUTPUT) CLK0, CLK0 tPLH Propagation delay low-to-high Qn, Qn 2 3 ns CLK1, CLK1 Propagation delay high-to-low CLK0, CLK0 tPHL Qn, Qn 2 3 ns CLK1, CLK1 CLK0, CLK0 tduty Duty cycle Qn, Qn 45% 55% CLK1, CLK1 tsk(o) Output skew Any Qn, Qn 30 ps tsk(p) Pulse skew Any Qn, Qn 50 ps tsk(pp) Part-to-part skew Any Qn, Qn 600 ps tr Output rise time, 20% to 80%, RL = 100 Ω, CL = 5 pF Any Qn, Qn 350 ps tf Output fall time, 20% to 80%, RL = 100 Ω, CL = 5 pF Any Qn, Qn 350 ps CLK0, CLK0 fclk Max input frequency Any Qn, Qn 900 1100 MHz CLK1, CLK1 over recommended operating free-air temperature range, VDD = 2.5 V ±5% (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fMAX Maximum frequency of shift register 100 150 MHz tsu Setup time, clock to SI 2 ns th Hold time, clock to SI 1.5 ns tremoval Removal time, enable to clock 1.5 ns tw Clock pulse width, minimum 3 ns VIH Logic input high VDD = 2.5 V 2 V VIL Logic input low VDD = 2.5 V 0.8 V 4 Submit Documentation Feedback Copyright © 2002–2008, Texas Instruments Incorporated Product Folder Link(s) :CDCLVD110 |
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Description similaire - CDCLVD110VF |
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