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CDC582 Fiches technique(PDF) 7 Page - Texas Instruments

No de pièce CDC582
Description  3.3-V PHASE-LOCK LOOP CLOCK DRIVER
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

CDC582 Fiches technique(HTML) 7 Page - Texas Instruments

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CDC582
3.3V PHASELOCK LOOP CLOCK DRIVER
WITH DIFFERENTIAL LVPECL CLOCK INPUTS
SCAS446B − JULY 1994 − REVISED FEBRUARY 1996
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
fclock
Clock frequency
VCO is operating at four times the CLKIN/CLKIN frequency
25
50
MHz
fclock
Clock frequency
VCO is operating at double the CLKIN/CLKIN frequency
50
100
MHz
Input clock duty cycle
40%
60%
After SEL1, SEL0
50
Stabilization time†
After OE
50
µs
Stabilization time
After power up
50
µs
† Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay
and skew parameters given in the switching characteristics table are not applicable.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 15 pF (see Note 4 and Figures 1, 2, and 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
MAX
UNIT
Duty cycle
Y
45%
55%
fmax
100
MHz
Jitter(pk-pk)
CLKIN
Y
200
ps
tphase error‡
CLKIN
Y
−500
500
ps
tsk(o)‡
Y
0.5
ns
tsk(pr)‡
Y
1
ns
tr
1.4
ns
tf
1.4
ns
‡ The propagation delay, tphase error, is dependent on the feedback path from any output to the FBIN. The tphase error, tsk(o), and tsk(pr)
specifications are only valid for equal loading of all outputs.
NOTE 4: The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
LOAD CIRCUIT FOR OUTPUTS
tphase error
2 V
2.4 V
1.6 V
VOH
VOL
CLKIN
0.8 V
2 V
tr
tf
0.8 V
2 V
500
CL = 30 pf
(see Note A)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
1.5 V
CLKIN
2 V
NOTES: A. CL includes probe and jig capacitance.
B. The outputs are measured one at a time with one transition per measurement.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms


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