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CDC318ADLRG4 Fiches technique(PDF) 7 Page - Texas Instruments

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No de pièce CDC318ADLRG4
Description  1Line to 10Line Clock Driver
Download  14 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

CDC318ADLRG4 Fiches technique(HTML) 7 Page - Texas Instruments

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CDC318A
1LINE TO 18LINE CLOCK DRIVER
WITH I2C CONTROL INTERFACE
SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating conditions
PARAMETER
FROM
TO
TEST CONDITIONS
MIN
MAX
UNIT
A
Y
1.2
4.5
ns
tPLH
Low-to-high level propagation delay time
SCLOCK
SDATA
valid
VCC = 3.3 V ±0.165 V,
See Figure 3
2
µs
tPLH
Low-to-high level propagation delay time
SDATA
Y
VCC = 3.3 V ±0.165 V,
See Figure 3
150
ns
A
Y
1.2
4.5
ns
tPHL
High-to-low level propagation delay time
SCLOCK
SDATA
valid
VCC = 3.3 V ±0.165 V,
See Figure 3
2
µs
tPHL
High-to-low level propagation delay time
SDATA
Y
VCC = 3.3 V ±0.165 V,
See Figure 3
150
ns
tPZH
Enable time to the high level
OE
Y
1
7
ns
tPZL
Enable time to the low level
OE
Y
1
7
ns
tPHZ
Disable time from the high level
OE
Y
1
7
ns
tPLZ
Disable time from the low level
OE
Y
1
7
ns
tsk(o)
Skew time
A
Y
250
ps
tsk(p)
Skew time
A
Y
500
ps
tsk(pr)
Skew time
A
Y
1
ns
tr
Rise time
Y
0.5
2.2
ns
tr
Rise time (see Note 5 and
SDATA
CL = 10 pF
6
ns
tr
Rise time (see Note 5 and
Figure 3)
SDATA
CL = 400 pF
950
ns
tf
Fall time
Y
0.5
2.3
ns
tf
Fall time (see Note 5 and
SDATA
CL = 10 pF
20
ns
tf
Fall time (see Note 5 and
Figure 3)
SDATA
CL = 400 pF
250
ns
NOTE 5: This parameter has a lower limit than BUS specification. This allows use of series resistors for current spike protection.
ESD information
ESD MODELS
LIMIT
Human Body Model (HBM)
2.0 kV
Machine Model (MM)
200 V
Charge Device Model (CDM)
2.0 kV
thermal information
CDC318A 48-PIN SSOP
THERMAL AIR FLOW (CFM)
UNIT
CDC318A 48-PIN SSOP
0
150
250
500
UNIT
RθJA
High K
62
56
54
51
°C/W
RθJA
Low K
95
71
65
58
°C/W
RθJC
High K
36
°C/W
RθJC
Low K
38
°C/W


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