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CDC318ADLRG4 Fiches technique(PDF) 2 Page - Texas Instruments |
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CDC318ADLRG4 Fiches technique(HTML) 2 Page - Texas Instruments |
2 / 14 page CDC318A 1LINE TO 18LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE INPUTS OUTPUTS OE A 1Y0−1Y3 2Y0−2Y3 3Y0−3Y3 4Y0−4Y3 5Y0−5Y1 L X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z H L L L L L L H H H† H† H† H† H† † The function table assumes that all outputs are enabled via the appropriate I2C configuration register bit. If the output is disabled via the appropriate configuration bit, then the output is driven to a low state, regardless of the state of the A input. logic diagram (positive logic) 1Y0−1Y3 2Y0−2Y3 3Y0−3Y3 4Y0−4Y3 5Y0−5Y1 OE SDATA SCLOCK A I2C Register Space I2C 38 24 25 11 4, 5, 8, 9 13, 14, 17, 18 31, 32, 35, 36 40, 41, 44, 45 21, 28 18 / |
Numéro de pièce similaire - CDC318ADLRG4 |
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Description similaire - CDC318ADLRG4 |
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