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CD74HCT574QPWRQ1 Fiches technique(PDF) 1 Page - Texas Instruments |
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CD74HCT574QPWRQ1 Fiches technique(HTML) 1 Page - Texas Instruments |
1 / 16 page CD74HCT574Q1 HIGHSPEED CMOS LOGIC OCTAL DTYPE FLIPFLOP 3STATE, POSITIVEEDGE TRIGGERED SCLS570A − FEBRUARY 2004 − REVISED APRIL 2008 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Qualified for Automotive Applications D Buffered Inputs D Common 3-State Output-Enable Control D 3-State Outputs D Bus-Line Driving Capability D Typical Propagation Delay (Clock to Q): 15 ns at VCC = 5 V, CL = 15 pF, TA = 255C D Fanout (Over Temperature Range) − Standard Outputs ... 10 LSTTL Loads − Bus Driver Outputs ... 15 LSTTL Loads D Balanced Propagation Delay and Transition Times D Significant Power Reduction Compared to LSTTL Logic ICs D VCC Voltage = 4.5 V to 5.5 V D Direct LSTTL Input Logic Compatibility, VIL = 0.8 V (Max), VIH = 2 V (Min) D CMOS Input Compatibility, Il v 1 mA at VOL, VOH description/ordering information The CD74HCT574 is an octal D-type flip-flop with 3-state outputs and the capability to drive 15 LSTTL loads. The eight edge-triggered flip-flops enter data into their registers on the low-to-high transition of the clock (CP). The output enable (OE) controls the 3-state outputs and is independent of the register operation. When OE is high, the outputs are in the high-impedance state. ORDERING INFORMATION{ TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40 °C to 125°C SOIC − M Tape and reel CD74HCT574QM96Q1 HCT574Q −40 °C to 125°C TSSOP − PW Tape and reel CD74HCT574QPWRQ1 HCT574Q † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. Copyright 2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. M OR PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OE D0 D1 D2 D3 D4 D5 D6 D7 GND VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CP |
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