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CD74ACT297 Fiches technique(PDF) 2 Page - Texas Instruments |
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CD74ACT297 Fiches technique(HTML) 2 Page - Texas Instruments |
2 / 18 page CD74ACT297 DIGITAL PHASE-LOCKED LOOP SCHS297D – AUGUST 1998 – REVISED JUNE 2002 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) This device performs the classic first-order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked loop (DPLL) is not affected by VCC and temperature variations, but depends solely on accuracies of the K clock (K CLK), increment/decrement clock (I/D CLK), and loop propagation delays. The I/D clock frequency and the divide-by-N modulos determine the center frequency of the DPLL. The center frequency is defined by the relationship fc = I/D clock/2N (Hz). Increment/Decrement Circuit Modulo K Counter K CLK I/D CLK φB φA2 D/U ENCTR φA1 DC B A 14 15 1 2 4 6 3 5 9 10 13 7 11 12 J K ECPD OUT XORPD OUT I/D OUT Modulo Controls Figure 1. Simplified Block Diagram |
Numéro de pièce similaire - CD74ACT297 |
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Description similaire - CD74ACT297 |
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