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DAC7545JP Fiches technique(PDF) 10 Page - Texas Instruments |
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DAC7545JP Fiches technique(HTML) 10 Page - Texas Instruments |
10 / 13 page www.ti.com PACKAGE OUTLINE C TYP 10.63 9.97 2.65 MAX 18X 1.27 20X 0.51 0.31 2X 11.43 TYP 0.33 0.10 0 - 8 0.3 0.1 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 13.0 12.6 B 7.6 7.4 4220724/A 05/2016 SOIC - 2.65 mm max height DW0020A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. 1 20 0.25 C A B 11 10 PIN 1 ID AREA NOTE 4 SEATING PLANE 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.200 |
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